Specifications

VLSI

Solution

VS1053b

VS1053B

10. VS1053B REGISTERS

10.8 Interrupt Registers

Interrupt registers, preﬁx INT

Reg Type Reset Abbrev[bits] Description

0xC01A rw 0 ENABLE[7:0] Interrupt enable

0xC01B w 0 GLOB DIS[-] Write to add to interrupt counter

0xC01C w 0 GLOB ENA[-] Write to subtract from interrupt counter

0xC01D rw 0 COUNTER[4:0] Interrupt counter

INT ENABLE controls the interrupts. The control bits are as follows:

INT ENABLE bits

Name Bits Description

INT EN TIM1 7 Enable Timer 1 interrupt

INT EN TIM0 6 Enable Timer 0 interrupt

INT EN RX 5 Enable UART RX interrupt

INT EN TX 4 Enable UART TX interrupt

INT EN SDI 2 Enable Data interrupt

INT EN SCI 1 Enable SCI interrupt

INT EN DAC 0 Enable DAC interrupt

Note: It may take upto 6 clock cycles before changing INT ENABLE has any effect.

Writing any value to INT GLOB DIS adds one to the interrupt counter INT COUNTER and effectively

disables all interrupts. It may take upto 6 clock cycles before writing to this register has any effect.

Writing any value to INT GLOB ENA subtracts one from the interrupt counter (unless INT COUNTER

already was 0). If the interrupt counter becomes zero, interrupts selected with INT ENABLE are re-

stored. An interrupt routine should always write to this register as the last thing it does, because in-

terrupts automatically add one to the interrupt counter, but subtracting it back to its initial value is the

responsibility of the user. It may take upto 6 clock cycles before writing this register has any effect.

By reading INT COUNTER the user may check if the interrupt counter is correct or not. If the register

is not 0, interrupts are disabled.

Version 1.01, 2008-05-22 68