User Guide Power MIDAS M5000 Series Single Board Computer
Notice The information in this document is subject to change without notice and should not be construed as a commitment by VMETRO. While reasonable precautions have been taken, VMETRO assumes no responsibility for any errors that may appear in this document. Trademarks Trademarked names appear throughout this document.
Warranty VMETRO products are warranted against defective materials and workmanship within the warranty period of 1 (one) year from date of invoice. Within the warranty period, VMETRO will, free of charge, repair or replace any defective unit covered by this warranty. A Return to Manufacturer Authorization (RMA) number should be obtained from VMETRO prior to return of any defective product. With any returned product, a written description of the nature of malfunction should be enclosed.
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Preface Introduction The VMETRO MIDAS M5000 series is a single-board computer (SBC) built in a 6U VMEbus form factor based on the AMCC PPC440GX PowerPC processor. This document describes the M5000 hardware. The chapters are summarized below: • • • • • • Product Overview: provides a brief description of the M5000. Installation and Hardware description: Installation procedures. Processor Subsystem: Describes the system surrounding Processor.
IEC Prefixes for binary multiples Symbol Name Origin Derivation Size Ki Kibi Kilo binary kilo 1024 bytes Mi Mebi Mega binary mega 1 048 576 bytes Gi Gibi Gig binary giga 1 073 741 824 bytes Quality Assurance VMETRO is dedicated to supplying our customers with products and services of the highest quality. We therefore, continually review and assess our products and services with the aim to improve the processes involved in the development of our world-class products.
Contents 1 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Main features: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Main Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Processor Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PMC Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . .
RJ45 Ethernet Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Processor Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Primary PCI Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 AMCC 440GX PowerPC Embedded Processor . . . . . . . . . . . . . . .
IDSEL Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3 Tundra Universe IID PCI-to-VME Bridge . . . . . . . . . . . . . . . . . . . . . . 44 Power-up / Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.4 Mercury PXB++ PCI-to-RACE++ Bridge . . . . . . . . . . . . . . . . . . . . . . 45 Power-up / Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.
APPENDIXES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 A PLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Miscellaneous PLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 INTERRUPT Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 B Universe IID Configuration Examples . . . . . . . . . . . . . . . . . . . . . . .
Figures FIGURE 1-1 FIGURE 1-2 FIGURE 1-3 FIGURE 2-1 FIGURE 2-2 FIGURE 2-3 FIGURE 2-4 FIGURE 2-5 FIGURE 3-1 FIGURE 3-2 FIGURE 3-3 FIGURE 4-1 FIGURE 5-1 FIGURE 6-1 FIGURE 6-2 FIGURE 6-3 FIGURE 6-4 FIGURE 6-5 FIGURE 7-1 FIGURE B-1. FIGURE B-2. Component Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Processor Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 PMC Subsystem . . . . . . . . . . .
xii M5000 Series: User Guide Issued June 20, 2007 5:23
Tables TABLE 2-1.Default Jumper and Switch settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TABLE 2-2.PCI-X to PCI-X Bridges SW2, SW9, SW8 settings . . . . . . . . . . . . . . . . . . . . . . . . . TABLE 2-3.PCI-to-VME bridge SW11 settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TABLE 2-4.PCI-to-VME bridge SW5 settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TABLE 2-5.PCI-to-VME bridge SW3 settings. .
TABLE B-2. VME Slave image 0 - setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 TABLE B-3.VME Slave image 1 - setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 TABLE B-4.VME Slave image 2 - setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 TABLE B-5.Initialization sequence for VMEbus slave image config. example. . . . . . . . . . . . . . 84 TABLE B-6.PCI slave image 0 setup.. . .
1 Product Overview The M5000 series is part of the next generation of boards in the MIDAS family. As for the previous generations, the M5000 series focuses on high-performance data buffering and flexible data flows between I/O ports. I/Os are provided through front panel connectors and P2 and P0 backplane connectors.
Product Overview 1.1 Main features: • A PowerPC processor subsystem (440GX from IBM) with up to 256MiB local DDR-SDRAM memory, 32MiB of FLASH memory, four Ethernet ports (two 10/100/1000Mbps and two 10/ 100Mbps) and two serial ports. • Two standard PPMC sites located on separate PCI segments (64-bit, 33/66MHz PCI, 66/100/ 133MHz PCI-X).
Main Components 1.2 Main Components Processor Subsystem The processor subsystem is built around the AMCC 440GX integrated processor, the QLOGIC ISP2312 dual Fibre Channel I/O Controller and the PCI6540 PCI-X to PCI-X bridge. The Processor Subsystem is located on the Primary PCI segment (PCI-X).
Product Overview PCI6540 PCIX-to-PCIX Bridge The PCI6540 provides a 64-bit PCI-X to PCI-X bridge designed for high performance, high availability applications, in PCI-X to PCI-X conversion, bus expansions, frequency conversions from faster PCI-X to slower PCI-X or from slower PCI-X to faster PCI-X bus, address remapping, high availability and universal system-to-system bridging. The PLX bridge is normally used as a transparent bridge, with its primary interface connected to the Processor PCI-X Segment.
Main Components • • • • • 33MHz, 32/64-bit PCI 66MHz, 32/64-bit PCI 66MHz, 32/64-bit PCI-X 100MHz, 32/64-bit PCI-X 133MHz, 32/64-bit PCI-X PCI-X is supported according to the VITA 39 PCI-X Auxiliary Standard For PMCs and Processor PMCs. Both PMC sites support either 3.3V or 5V signaling on VIO. The choice is determined by mounting options (resistors and voltage key/pin) and can only be modified by VMETRO. The default setting when shipped is 3.3V.
Product Overview PXB ++ PLX 6540 PCI-X to PCI-X Bridge PCI/PCI X (33 133MHz, 64bit) UNIV IID PCI (33MHz, 64bit, 5V) MEZZ VME Interface The Tundra Universe IID PCI-to-VME Bridge is a PCI only component which provides VME accesses. Hardware configuration of the Universe IID is done entirely using micro switches. RACE++ Interface The Mercury PXB++ PCI-to-RACE++ Bridge is a PCI only component which provides RACE++ accesses.
Main Components JTAG Interfaces The JTAG chain is separated into three segments. One segment contains the CPLD devices, a second contains the AMCC 440GX processor and the last one contains the remaining JTAG capable chips. It is possible to connect to only the segments that are appropriate for a specific software tool. An adapter board is needed to connect to the correct taps of the chain, and to provide connectors that are compatible with the tools connector. For more information please contact VMETRO.
Product Overview 8 M5000 Series: User Guide Issued June 20, 2007
2 Installation and Hardware description Issued June 20, 2007 M5000 Series: User Guide 9
Installation and Hardware description 2.1 Before You Begin Precautions in Handling and Storage Static electricity can permanently damage your M5000. Prevent electrostatic damage by taking proper precautions. • Make sure your body is grounded when coming into contact with the board by wearing an antistatic wrist strap. • If an anti-static wrist strap is not available, touch a grounded surface, such as the bare metal chassis, before touching the M5000.
Installing PMC Modules 2.2 Installing PMC Modules The M5000 is shipped with two PMC filler panels mounted in the front panel. They act as EMC shielding in unused PMC positions. Before installing a PMC module, the filler panel(s) must be removed. This is done by pushing them out from the backside of the front panel.
Installation and Hardware description 2.
Switches and Jumper Settings Default Jumper and Switch Settings The factory settings of the jumpers and switches are shown in Table 2-1: TABLE 2-1. Default Jumper and Switch settings Jumper/switch Position Description JP1 Inserted on left side on R models.
Installation and Hardware description Each switch is has the settings described in Table 2-2. TABLE 2-2. PCI-X to PCI-X Bridges SW2, SW9, SW8 settings Switch Function 1 Port Priority Boot The switch is connected to the P_BOOT pin on the bridge. Non-Transparent Mode: the primary/secondary port has boot priority when the switch is ON/ OFF Transparent Mode: Not Used. 2 Serial EEPROM Access Enable ON enables the EEPROM accesses.
Switches and Jumper Settings PCI-to-VME Bridge The PCI-to-VME bridge is configured using the switches SW5, SW3 and SW11. TABLE 2-3. PCI-to-VME bridge SW11 settings Switch Function 1 SYSFAIL Assertion SYSFAIL is not asserted when the switch is ON. SYSFAIL is asserted asserted when the switch is OFF 2 VME64 AutoId AutoId is enabled when the switch is ON AutoId is disabled when the switch is OFF TABLE 2-4.
Installation and Hardware description PCI to RACEway Bridge The PCI to RACEway bridge is configured using switch SW7. TABLE 2-6. RACEway-to-PCI Switch Function 1 Operating Mode bridge SW7 settings The bridge is configured in bridge mode/endpoint mode when the switch is ON/OFF. This switch is connected to the pin RES_PROM_P on the bridge. Leave open. 2 Serial EEPROM Autoload ON enables the Serial EEPROM Autoload process.
Switches and Jumper Settings PCI-X Capability Selection for PMC Slots The PCI-X Capability Selection is performed using the switches SW1 and SW4. • Switch 1 configures PMC#2 bus • Switch 4 configures PMC#1 bus TABLE 2-9.
Installation and Hardware description 2.4 Installing the M5000 into the VME Chassis Slot Selection Warning! Do not install the board into a powered system! You can install the M5000 board into any VMEbus slot in a 6U VMEbus chassis as long as the daisy chains for the bus grant and interrupt acknowledge signals are continuous, from the left-most slot, to the slot in which the M5000 board is installed. The metal strip along the card edge is for electrostatic-discharge.
Installing the M5000 into the VME Chassis Although the M5000 board may increase the system power consumption by driving the VME bus, the additional power is not included in the numbers below, since the additional power is dissipated outside the board. Furthermore, the VME traffic pattern, and the M5000's share of the VME bus is highly application dependent. TABLE 2-10. M5000 Issued June 20, 2007 Power Consumption Model Idle Power Consumprion Active Power Consumption M5210-EF0 13.5 W 15.
Installation and Hardware description 2.5 Environmental Specifications VMETRO offers ruggedized versions of selected models of the PowerMIDAS M5000s that are characterized for extended temperature range, shock, vibration, altitude and humidity. These boards are equipped with extra and/or special hardware to improve tolerance against shock and vibration. Table 2-11 shows the environmental specifications for both commercial and rugged models of the PowerMIDAS M5000 series.
Front Panel Connectors 2.6 Front Panel Connectors Figure 2-2 shows the front panel connectors on the M5000. FIGURE 2-2 Front Panel connections Ethernet Eth Duplex Link FC1 VM ETRO PMC #2 1 10/100 Ethernet Port 2 PMC #1 FC2 1 2 Serial Fibre Channel Ports Power Fail Serial Port PMC # 2 Site PMC # 1 Site Various configurations of the IO connectors are possible depending on the model of M5000 you have ordered. Figure 2-3 shows the possible configurations.
Installation and Hardware description Fibre Channel Port LEDS TABLE 2-12. Fibre Channel Port LEDS Amber LED Green LED Power On On Steady On Steady Loss of Sync Flash at half-second interavls OFF Signal Acquired On Steady OFF Online OFF On Steady System Error (8002h) Flash at half-second intervals Flash at half-second intervals RS232 Connector and cables The processor has its own dedicated serial connections.
Front Panel Connectors FIGURE 2-4 RS232 pinout 1 2 7 3 To Board 6 5 4 M5x10-RS232/RS422 DB9 Female RS232_Rx RS232_Tx Pin 2 Pin 1 Pin 2 Pin 3 RxD1 TxD1 GND Pin 7 Pin 5 GND RS422_Rx+ RS422_RxRS422_Tx+ RS422_Tx- Pin 5 Pin 6 Pin 3 Pin 4 Port#1 RS-232 DB9 Female LEMO Male Pin 7 Pin 6 Pin 2 Pin 1 Rx+ RXTx+ TX- Pin 5 GND Port#2 RS-422 Red Housing To Board M5x10-2xRS232 DB9 Female RxD1 TxD1 Pin 2 Pin 1 Pin 2 Pin 3 RxD1 TxD1 GND Pin 7 Pin 5 GND RxD2 TxD2 Pin 6 Pin 5 Port#1 RS-23
Installation and Hardware description RJ45 Ethernet Connector The M5000 board has an RJ45 type connector for connecting to Ethernet. FIGURE 2-5 Ethernet connector Pin 1 Pin 8 Pin 1: TxD+ Pin 2: TxDPin 3: RxD+ Pin 6: RxD- To connect to ethernet, cables with RJ45 connectors must be used. Cat. 5 cables are recommended.
3 Issued June 20, 2007 Processor Subsystem M5000 Series: User Guide 25
Processor Subsystem 3.1 Introduction FIGURE 3-1 Processor Subsystem Block Diagram SRAM PCI/PCI -X (33- 133MHz, 64bit) PLX 6540 PCI - X to PCI - X Bridge PCI- X (64 - bit / 133MHz) SPROM 10/100MBit 10/100/1000MBit RS232 Console QLOGIC ISP2312 Dual FC Host Adapter FLASH 2Gbits/s FC SPROM SMII IBM 440GX Processor RGMII SPROM FLASH RS232 / RS422 64-bit 133MHz RS232 / RS422 Console / DCRsi DDR SDRAM 256 Primary PCI Segment The Primary PCI Segment is a 64-bit/133MHz PCI-X bus.
AMCC 440GX PowerPC Embedded Processor 3.2 AMCC 440GX PowerPC Embedded Processor Designed specifically to address high-end embedded applications, the PowerPC 440GX (PPC440GX) provides a high-performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation.
Processor Subsystem Link Configuration The four Ethernet links are configured the following way: • The first two MAC interfaces are always configured as SMII (Serial Media Independent Interface). The media interfaces are always configured in the 10/100-TX mode • The third and fourth MAC interfaces are always configured as RGMII (Reduced Gigabit Media Independent Interface).
AMCC 440GX PowerPC Embedded Processor TABLE 3-2.
Processor Subsystem The 440GX PowerPC processor has access to the four temperature sensors on its secondary I2C bus.
QLOGIC ISP2312 Dual Fibre Channel Controller 3.3 QLOGIC ISP2312 Dual Fibre Channel Controller The ISP2312 is a highly integrated single-chip, dual-channel, bus master, Fibre Channel processor that targets storage, clustering, and networking applications. This chip connects a conventional PCI or PCI-X bus to one or two 1.062 or 2.125 Gbps Fibre Channel ports connected to fabric, single arbitrated loop or point-to-point topologies.
Processor Subsystem 3.4 PCI-X to PCI-X Bridges The PLX6540 64-bit PCI-X to PCI-X bridge is designed for high performance, high availability applications, in PCI-X to PCI conversion, bus expansions, frequency conversions from faster PCIX to slower PCI-X or from slower PCI-X to faster PCI-X bus, address remapping, high availability hot swap and universal system-to-system bridging.
PCI-X to PCI-X Bridges Secondary Interface The secondary interface of the PCI6540 is connected to the first PMC site (PMC#1) and the primary interface of another PCI6540 bridge.
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4 Issued June 20, 2007 PMC Subsystem M5000 Series: User Guide 35
PMC Subsystem 4.1 Introduction The PMC subsystem is composed of two 3.3V signalling PMC sites and is located on two PCI(-X) segments called the Secondary and Tertiary PCI Segments. The connection between the two PCI(X) segments is provided by a PCI-X to PCI-X bridge.
Secondary and Tertiary PCI Segments 4.2 Secondary and Tertiary PCI Segments PCI Mode and Speed Configuration The PCIXCAP and M66EN pins of a PMC module determine which clock speed and protocol (PCI vs. PCI-X) can be used on the segment. There are five detectable modes of operation: 33/66MHz PCI and 66/100/133MHz PCI-X.
PMC Subsystem • AD[20] is used for the PCI6540 P2P Primary Side IDSEL (PCI6540 closer to the Extension Subsystem) Processor PMC Support The Processor PMC standard adds several extensions to the PMC standard: • Support for a second PCI device: Support for a second device requires an additional REQ/ GNT pair and an additional IDSEL signal.
PCI6540 PCIX-to-PCIX Bridge 4.3 PCI6540 PCIX-to-PCIX Bridge This Bridge has been discussed in “PCI-X to PCI-X Bridges” on page 32. What follows are details appropriate for this particular bridge. Power-up / Reset Configuration Options PCI-X Capability Both primary and secondary interfaces can be run in PCI or PCI-X modes. See “PCI-X Capability Selection for PMC Slots” on page 11.
PMC Subsystem 4.4 PMC to VME connections PMC#1-P4 to VME-P2 In addition to the standard PCI(-X) bus, the PMC#1 site includes a connection between its P4 connector and the VME-P2 connector. This connection follows the ANSI/VITA 35-2000 standard (PMC-P4 pin out mapping to VME P0 and VME64x-P2). As for the PMC#1-P4 to VME-P2 connection, signals are routed as differential pairs. Note – PMC#1-P4 is not mounted on RACEway models.
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Extension Subsystem 5.1 Introduction The Extension Subsystem is composed of VME, RACEway and mezzanine connections. All the devices are located on a private 64-bit, 33MHz, 5V signaling, PCI only segment. This PCI segment is called the Quaternary PCI Segment. A PCI6540 universal PCI-X to PCI-X bridge connects the Quaternary PCI Segment with the Tertiary PCI Segment.
Quaternary PCI Segment 5.2 Quaternary PCI Segment The Quaternary PCI Segment is a 64-bit/33MHz PCI bus. Devices Three major devices are located on the Quaternary PCI Segment: • Tundra Universe IID PCI-to-VME bridge. • Mercury PXB++ PCI-to-RACE++ bridge. • PCI6540 PCI-X to PCI-X bridge. Arbitration The built in arbiter of the PCI6540 bridge is used to arbitrate this segment.
Extension Subsystem 5.3 Tundra Universe IID PCI-to-VME Bridge The Tundra Universe II is the industry's leading high performance PCI-to-VMEbus interconnect. Universe II is fully compliant with the VME64 bus standard, and tailored for the next-generation of advanced PCI processors and peripherals. With a zero-wait state implementation, multi-beat transactions, and support for bus-parking, Universe II provides high performance on the PCI bus.
Mercury PXB++ PCI-to-RACE++ Bridge 5.4 Mercury PXB++ PCI-to-RACE++ Bridge The PXB++ implements the functions required to bridge the PCI local bus with the RACEway Interlink crossbar fabric. The PXB++ performs all necessary address translation and routing functions to support high speed transfers between the local PCI bus and either native RACEway interfaces or remote PCI buses which also use PXB++ interfaces. This architecture allows PXB++ to be used for two distinct types of applications.
Extension Subsystem 5.5 Mezzanine Connector The mezzanine connector extends the Quaternary PCI Segment to a MEZZ-x500F type mezzanine which contains 3 PMC slots.
PCI6540 PCI-X to PCI-X Bridge 5.6 PCI6540 PCI-X to PCI-X Bridge More information about the PCI-X to PCI-X Bridge processor has been discussed in “PCI-X to PCI-X Bridges” on page 32. Power-up / Reset Configuration Options PCI-X Capability • Primary port: XCAP signal is setup at boot-up by the configuration of PCIXCAP, M66EN signals and configuration switches. • Secondary port: this PCI segment is setup to run in the 64-bit/33MHz PCI mode.
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6 Mezzanine PMC Carrier Precautions in Handling and Storage Static electricity can cause permanent damage. Prevent electrostatic damage by taking proper precautions. • Make sure your body is grounded when coming into contact with the board by wearing an anti-static wrist strap. • If an anti-static wrist strap is not available, touch a grounded surface, such as the bare metal chassis, before touching the M52xx and Mezzanine PMC Carrier board.
Mezzanine PMC Carrier 6.
Board Layout 6.
Mezzanine PMC Carrier 6.3 Installing PMC Modules onto the PMC Carrier The M5000 is shipped with two PMC filler panels mounted in the front panel. They act as EMC shielding in unused PMC positions. Before installing a PMC module, the filler panel(s) must be removed. This is done by pushing them out from the backside of the front panel Warning! Be extremely careful when inserting screws to secure PMC modules.
Installing PMC Modules onto the PMC Carrier FIGURE 6-3 Mounting screws for the PMC Carrier Item 800 Item 800 Item 800 PMC #2 PMC #1 Item 807 Item 800 Item 807 Item 807 PMC #3 Item 800 PMC #4 Item 807 PMC #5 Item 800 Item 800 Item 800 Step 2: Install the PMC boards onto the PMC Carrier 1. Place the Mezzanine PMC Carrier on a smooth static protected work surface. 2. Install the PMC modules in the PMC Carrier.
Mezzanine PMC Carrier FIGURE 6-4 Mounting the PMC modules PMC Module PMC #3 PMC #4 PMC Module PMC #5 PMC Module Step 3: Reassemble the unit 1. Fasten the PMC Carrier board to the M52xx using screws as shown in Figure 6-3 PMC Carrier Daisy-Chain The P1 connector of the PMC Carrier board provides a daisy-chain bypass for the signals BG[3:0]* and IACKIO*. Therefore, no action is required to keep the daisy-chain operating through the PMC Carrier board.
Functional Description 6.4 Functional Description System Overview The Mezzanine PMC Carrier has 3 PMC slots which adds an extra PCI bus to bridge the two existing busses on the M52xx board. There are two bridges 64bit wide and operate at 33Mhz. These bridges provide a connection from the M52xx bus to the PMC Carrier bus. Arbitration on the mezzanine bus The secondary bridge is responsible as arbiter for the mezzanine bus. TABLE 6-1.
Mezzanine PMC Carrier Interrupt routing The PMC Carrier board has four interrupts from each of the three PMCs. These are routed (multiplexed) to the M52xx board via an interrupt routing PLD (Programmable Logic Device). The PMC Carrier board will distribute these interrupts to the base board interrupt destinations according to the routing tables in “Interrupt Routing” on page 66. FIGURE 6-5 Carrier Board Interrupts PMC#3 Interrupt routing PLD PMC#4 MezzIRQ 0-3 To PowerMIDAS board PMC#5 TABLE 6-3.
Functional Description Debug Functions The PMC Carrier board has some additional circuitry which is not normally used, but can be used for very low-level debugging. This circuitry includes; • Two debug LEDs. • A status register where the value of the interrupt signals from the PMC slots are available. Both functions are accessed through the use of the GPIO pins on one of the P2P bridges. Contact VMETRO for more details.
Mezzanine PMC Carrier 6.5 VME Connectors on MEZZ-x500 VME P1 Connector on MEZZ-x500F TABLE 6-4.
VME Connectors on MEZZ-x500 VME P2 Connector on MEZZ-x500F TABLE 6-5.
Mezzanine PMC Carrier 6.6 PMC Connector Pinouts on PMC Carrier (MEZZ-x500F) PMC Connector Pinouts Jn1, Jn2 and Jn3 for all PMC slots on MEZZ-x500F The pinouts for PMC connectors Jn1, Jn2 and Jn3 on the MEZZ-x500F (all three PMC slots) are the same as for the PMC connectors Jn1, Jn2 and Jn3 on the M52xx board. See “PMC Connector Pinout” on page 103 for pinout description.
PMC Connector Pinouts on PMC Carrier (MEZZ-x500F) PMC Connector Pinouts - Jn4 for PMC slot 4 on MEZZ-x500F Jn4 64 Bit PCI TABLE 6-6.
Mezzanine PMC Carrier PMC Connector Pinouts - Jn4 for PMC slot 5 on MEZZ-x500F Jn4 64 Bit PCI TABLE 6-7.
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Miscellaneous Functions 7.1 JTAG Chain Chain Topology The JTAG Chain is divided into three segments: • Processor • CPLDs • Other JTAG devices Each segment is used for a specific set of similar devices, and can be accessed separately from the remaining parts of the JTAG chain. This allows tools that only support certain devices to be used by only accessing the segment with supported devices. For more information please contact VMETRO.
Reset Network 7.2 Reset Network The board reset network is centralized around the reset PLD. Output reset signals are routed first to the reset PLD before being propagated to the other board components. The primary sources of reset are the power-up reset controller and reset button. Other sources are various software resets from the processor, PCI-X to PCI-X bridges, VME reset, RACEway reset and PMC modules etc.
Miscellaneous Functions 7.3 Interrupt Routing In order to support a flexible interrupt routing mechanism, all interrupt source and destination signals are routed to a PLD which provides the actual routing between sources and destinations: FIGURE 7-1 Interrupt Routing PCIX-to-PCIX Bridge Dual FC Host Adapter P,S PMC A,B, C,D PMC A,B, C,D MEZZ A,B, C,D A,B A,B, C,D PCI-to-RACE++ Bridge Interrupt Routing CPLD i0,i1 i2..i7 X P0..
Interrupt Routing Interrupt routing for PPMC#1 Source PPMC2 MEZZ PXB++ Universe Destination A,B,C,D A,B,C,D A,B,C,D A A,C B B,D A,C C B,D A,C D B,D PPC I0,I1 X X I0,I1 P2P P2P P2P Bridge 1 Bridge 2 Bridge 3 P,S P,S P,S S P P S P,S Interrupt routing for Universe II Source PPMC1 PPMC2 MEZZ PXB++ Destination A,B,C,D A,B,C,D A,B,C,D A,B,C,D A,C i2 i3 A,C i4 B,D A,C i5 B,D A,C i6 B,D i7 B,D Issued June 20, 2007 M5000 Series: User Guide PPC X P2P P2P P2P Bridge 1 Bridge 2 Bridge 3 P,S P,S P
Miscellaneous Functions Interrupt routing for PowerPC processor Source PPMC1 PPMC2 MEZZ Universe PBX++ Destination A,B,C,D A,B,C,D A,B,C,D A,C p0 A,C p1 B,D p2 p3 B,D p4 p5 p6 p7 A p8 p9 B C p10 D I0,I1 A,B,C,D Eth E FC Controller GE0, GE1 A,B Gig Eth A B A,C B,D GE0 I0 I1 GE1 E Temperature Sensors There are several temperature sensors located on the board. One is close to the bottom of the board, one close to the top of the board and two located in the middle of the board.
Power Supplies 7.4 Power Supplies The main sources of power are 5V and ±12V supplied by the VME backplane. The 5V power source is used to generate the required component voltages, ±12V is routed directly to the PMC sites.
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A Issued June 20, 2007 PLD Registers M5000 Series: User Guide 73
PLD Registers A-1 Miscellaneous PLD Registers The PLD registers can be accessed by the processor in following address range: TABLE A-1.
Miscellaneous PLD Registers PPC_BOOT 0 PPC_BOOT_SPROM_WE# PowerPC Boot SPROM devices are write-protected (1) or enabled (0) (Read-Only) 1 PPC_SPROM_WE# PowerPC MFS SPROM device is write-protected (1) or enabled (0) (Read-Only) 2 PPC_FLASH_MON_WE# PowerPC FLASH device (Monitor part) is write-protected (1) or enabled (0) (Read-Only) 3 PPC_FLASH_WE# PowerPC FLASH device is write-protected (1) or enabled (0) (Read-Only) 4 FC_FLASH_WE# QLOGIC ISP2312 FLASH device is write-protected (1) or enabled
PLD Registers PCI_CFG 76 7 PMC2_PCIX PMC#2 PCI(-X) Bus Mode (Read-Only): set to 1 if PCI-X mode detected on PCI(-X) bus where PMC site #2 is located, 0 otherwise 6 PMC1_PCIX PMC#1 PCI(-X) Bus Mode (Read-Only): set to 1 if PCI-X mode detected on PCI(-X) bus where PMC site #1 is located, 0 otherwise 5 PMC2_CLK1 PMC#2 PCI(-X) Bus Clock Speed Bit 1 (Read-Only): set to 1 if clock speed detected on PCI(-X) bus where PMC site #2 is located is over 66MHz, 0 otherwise 4 PMC2_CLK0 PMC#2 PCI(-X) Bus Cloc
Miscellaneous PLD Registers INTERRUPT Registers Address is offset from PLD base Address. TABLE A-3.
PLD Registers 78 M5000 Series: User Guide Issued June 20, 2007
B Universe IID Configuration Examples Issued June 20, 2007 M5000 Series: User Guide 79
Universe IID Configuration Examples B-1 General Information Note – The 'Universe IID' PCI-VME Bridge, performs byte swapping of the data lanes on all transactions between VMEbus and PCI bus. This is also the case for accesses to the internal registers. The internal register bank is located on the 'PCI side' of the byte swapping. This means that when registers are read or written from the VMEbus, all bytes are shuffled (compared to the bit numbering used in the Universe IID User Manual).
VMEbus Slave Images B-2 VMEbus Slave Images PCI Master Enable In addition to the configuration registers for the VMEbus slave images, one control register bit is essential for mapping VMEbus cycles to PCI bus cycles through the Universe IID. The PCI master enable ('BM') bit located in the PCI_CSR register space (offset: 0x004). This bit is set as default after power up. Some VMEbus Slave Image examples are shown in Figure B-1. FIGUREB-1.
Universe IID Configuration Examples VMEbus Register Access Image In this configuration example, the VMEbus Register Access Image is set up by use of the DIP switch and jumpers. TABLE B-1. VME_RAI Setup Action: Result: SW3-3 ON VME_RAI is enabled. SW3-1 ON, SW3-2 OFF VME_RAI is mapped in A24 address space. SW5 All OFF VME_RAI base address is set to 0x000000. SW11-2 OFF Disable Auto-slot ID protocol.
VMEbus Slave Images VMEbus Slave Image 1 The VMEbus Slave Image 1 is set up to map A24 accesses, in the address range 0x1000000x3FFFFF, from VMEbus to I/O Cycles on the PCI bus, with PCI addresses starting from 0x02100000. TABLE B-3. VME Slave image 1 - setup Write from VME PCI Data 1) Result: D:0x0000.1000 to A:0x000F18 0x0010.0000 Base Address set to 0x100000 D:0x0000.4000 to A:0x000F1C 0x0040.0000 Bound Address set to 0x400000 D:0x0000.0002 to A:0x000F20 0x0200.
Universe IID Configuration Examples Initialization Sequence By performing the list of cycles shown in the table below, the mapping for this configuration example is achieved. TABLE B-5. Initialization sequence for VMEbus slave image config. example. Write from VME PCI Data 1) Result: D:0x0000.0000 to A:0x000F04 0x0000.0000 VSI_0: Base Address set to 0x000000 D:0x0050.0000 to A:0x000F08 0x0000.5000 VSI_0: Bound Address set to 0x005000 D:0x0000.0000 to A:0x000F0C 0x0000.
PCI Slave Images B-3 PCI Slave Images The VME_RAI, described in the 'VMEbus Slave Images' section, is also utilized to set up PCI slave images in the examples below. PCI Target Enable - Memory & I/O Space In addition to the configuration registers for the PCI slave images, two control register bits are essential for mapping PCI bus cycles to VMEbus cycles through the Universe II.
Universe IID Configuration Examples PCI Slave Image 0 In this configuration example, the PCI Slave Image 0 is set up to map PCI I/O Space transactions, in the address range 0x0-0xFFF, to A24, D16 VMEbus cycles in the address range 0x1000-0x1FFF. TABLE B-6. PCI slave image 0 setup. Write from VME PCI Data 1) Result: D:0x0000.0000 to A:0x000104 0x0000.0000 Base Address set to 0x0000.0000 D:0x0010.0000 to A:0x000108 0x0000.1000 Bound Address set to 0x0000.1000 D:0x0010.0000 to A:0x00010C 0x0000.
PCI Slave Images PCI Slave Image 2 PCI Slave Image 2 is set up to map PCI Memory Space transactions, in the address range 0x4000.0000-0x5FFF.FFFF to A32, D64 VMEbus cycles, in the address range 0x0000.00000x1FFF.FFFF. TABLE B-8. PCI slave image 2 setup Write from VME PCI Data 1) Result: D:0x0000.0040 to A:0x00012C 0x4000.0000 Base Address set to 0x4000.0000 D:0x0000.0060 to A:0x000130 0x6000.0000 Bound Address set to 0x6000.0000 D:0x0000.00C0 to A:0x000134 0xC000.
Universe IID Configuration Examples 88 M5000 Series: User Guide Issued June 20, 2007
C VME64 Configuration ROM A VME64 Configuration SPROM is included in the board design. This SPROM is accessible from the processor via a set of I/O pins on the third PCIX-to-PCIX bridge. The general content layout is described in the ANSI/VITA 1.1.1997 specification (page 53).
VME64 Configuration ROM TABLE C-1. VME64 configuration ROM CROM Offset: 03 (VME CR/CSR Space) Offset Value 03 07 00 Length of ROM to be check summed. (MSB) 0B 00 Length of ROM to be check summed. (NMSB) 0F 1F Length of ROM to be check summed.
TABLE C-1. VME64 configuration ROM 3F Board ID 7-0 43 Revision ID 31-24 47 Revision ID23-16 4B Revision ID 15-8 4F Revision ID 7-0 53 00 Pointer to null terminated ASCII string.
VME64 Configuration ROM TABLE C-3.
TABLE C-5. Revision Issued June 20, 2007 ID Description Field Bits Description Family Specific Number 31-16 Reserved PCB Revision 15:12 PCB Revision number. (Start at 0xA and wrap from 0xF to 0x0) Reserved 11:8 '0000' ECO Level 7:0 ECO Level indicator.
VME64 Configuration ROM 94 M5000 Series: User Guide Issued June 20, 2007
D Issued June 20, 2007 VME Connector Pinout M5000 Series: User Guide 95
VME Connector Pinout D-1 General Description The abbreviation "NC" means Not Connected. The description "Jn4-1", Jn4-2", etc. used in the pinout table for P2 connector means the pins 1, 2, etc. on connector Jn4 on PMC slot 2.
VME P0 Connector for all models D-2 VME P0 Connector for all models Defined in DY4 StarLink PMC manual Pinout is compatable with DY4 Starlink PMC Module and Rear Transition Module. TABLE D-1.
VME Connector Pinout TABLE D-1.
VME P1 Connector for all models D-3 VME P1 Connector for all models TABLE D-2.
VME Connector Pinout D-4 VME P2 Connector for non-R model TABLE D-3.
VME P2 Connector for -R models D-5 VME P2 Connector for -R models TABLE D-4.
VME Connector Pinout 102 M5000 Series: User Guide Issued June 20, 2007
E Issued June 20, 2007 PMC Connector Pinout M5000 Series: User Guide 103
PMC Connector Pinout E-1 General Description “NC” means Not Connected. “PU” and “PD” mean that the connector pin is connected to +5V via a pull up resistor or to ground (GND) via a pull down resistor respectively. Connections to the VME P2 connector are denoted as P2-[row][pin]. Example: P2-D1 means connection to pin 1 in row D of the VME P2 connector. Pins that are PU, PD or NC for compliance with otherwise unsupported PCI signals have the PCI signal name appended in parenthesis.
PMC Connector Pinout - Jn1 for both PMC slots on all Models E-2 PMC Connector Pinout - Jn1 for both PMC slots on all Models Jn1 64 Bit PCI TABLE E-1.
PMC Connector Pinout E-3 PMC Connector Pinout - Jn2 for both PMC slots on all Models Jn2 64 Bit PCI TABLE E-2. Pinout for PMC connector Jn2 (both slots/all models) Pin# Signal Name Pin# Signal Name 1 +12V 2 PD (TRST#) 3 PD (TMS) 4 NC (TDO) 5 PD (TDI) 6 GND 7 GND 8 NC (PCI-RSVD) 9 NC (PCI-RSVD) 10 NC (PCI-RSVD) 11 PU (BUSMODE2#) 12 +3.3V 13 RST# 14 PD (BUSMODE3#) 15 3.
PMC Connector Pinout - Jn3 for both PMC Slots on all Models E-4 PMC Connector Pinout - Jn3 for both PMC Slots on all Models Jn3 64 Bit PCI TABLE E-3.
PMC Connector Pinout E-5 PMC Connector Pinout - Jn4 for PMC #1 & PMC #2 Jn4 64 Bit PCI PMC#1-to-VME P2 column only valid for non-Raceway models, PMC#2-to-VME P0 column only valid for P models. TABLE E-4.
PMC Connector Pinout - Jn4 for PMC #1 & PMC #2 TABLE E-4.
PMC Connector Pinout 110 M5000 Series: User Guide Issued June 20, 2007
F MTBF Values The Mean Time Between Failures (MTBF) values given here are calculated estimations representing the inherent reliability of the M5000 series SBCs. The prediction is done according to the Inherent Model in PRISM v1.5 (System reliability assessment tool). PRISM contains experience data and methods for predicting component reliability. Values are calculated for different environments but this does not mean that operation in this environment is supported.
MTBF Values TABLE F-1.
Ordering Information Models M5210-EF0 M5210-JEJ M5210-JFJ M5210-JFF M5210-GEG M5210-GFG M5210-GFF AMCC 440GX PowerPC Processor 133 MHz PCI-X PMC Positions High Speed Streaming Memory RJ45 10/100 Ethernet Optical 2Gb/s Fibre Channel RJ45 Gigabit Ethernet Optical Gigabit Ethernet 1 2 256MiB 1 1 - - 1 2 256MiB 1 - 2 - 1 2 256MiB - 1 2 - 1 2 256MiB - 2 1 - 1 2 256MiB 1 - - 2 1 2 256MiB - 1 - 2 1 2 256MiB - 2 - 1 In addition: -4 option: RS-422 instead of
Technical Support In order for us to provide fast technical support, please provide the following information: • Any modifications made to the default BSP. • Any changes to the default versions of the flash files, such as mmon.ini and vxbsp.ini. • Detailed description of all symptoms observed, including serial port output and analyzer trace files if applicable • Information about 3rd party drivers and HW that is used.
References The Fibre Channel Industry Association (FCIA) http://www.fibrechannel.org American National Standards Institute http://www.ansi.org Component Manufacturers Vendor Component Available documentation Tundra Universe II (VME-PCI Bridge) User Manual http://www.tundra.com Manual Addendum Device Errata Application Notes AMCC 440GX Processor http://www.amcc.com/ Processor Developers Manual Application Notes and more PLX Technology PCI 6540 PCI-X to PCI-X Bridge http://www.plxtech.
116 M5000 Series: User Guide Issued June 20, 2007
