User guide

87
Issued June 20, 2007
M5000 Series: User Guide
PCI Slave Images
PCI Slave Image 2
PCI Slave Image 2 is set up to map PCI Memory Space transactions, in the address range
0x4000.0000-0x5FFF.FFFF to A32, D64 VMEbus cycles, in the address range 0x0000.0000-
0x1FFF.FFFF.
1) This column shows write data for configuration from PCI
Initialization Sequence
By performing the list of cycles shown in the table below, the mapping for this configuration
example is achieved.
1) This column shows write data for configuration from PCI
TABLE B-8. PCI slave image 2 setup
Write from VME PCI Data 1) Result:
D:0x0000.0040 to A:0x00012C 0x4000.0000 Base Address set to 0x4000.0000
D:0x0000.0060 to A:0x000130 0x6000.0000 Bound Address set to 0x6000.0000
D:0x0000.00C0 to A:0x000134 0xC000.0000 Translation Offset set to 0xC000.0000
D:0x0001.C2C0 to A:0x000128 0xC0C2.0100 Enable Image, VAS=A32, VDW=D64, LAS=Mem.
Space, PGM=data, SUPER=non-priv, Posted Write
enabled, BLT allowed.
TABLE B-9. Initialization sequence for PCI slave image config. example.
Write from VME PCI Data 1) Result:
D:0x0700.8002 to A:0x000004 0x0200.0007 PCI Target Enable bits set. (this write cycle also sets the PCI master
enable bit if it is disabled, ref. VMEbus Slave Image section).
D:0x0000.0000 to A:0x000104 0x0000.0000 LSI_0: Base Address set to 0x0000.0000
D:0x0010.0000 to A:0x000108 0x0000.1000 LSI_0: Bound Address set to 0x0000.1000
D:0x0010.0000 to A:0x00010C 0x0000.1000 LSI_0: Translation Offset set to 0x0000.1000
D:0x0110.4180 to A:0x000100 0x8041.1001 LSI_0: Enable Image, VAS=A24, VDW=D16, LAS=I/O Space,
PGM=data, SUPER=supervisor, other options disabled.
D:0x0000.0010 to A:0x000118 0x1000.0000 LSI_1: Base Address set to 0x1000.0000
D:0x0000.0030 to A:0x00011C 0x3000.0000 LSI_1: Bound Address set to 0x3000.0000
D:0x0000.0010 to A:0x000120 0x1000.0000 LSI_1: Translation Offset set to 0x1000.0000
D:0x0001.82C0 to A:0x000114 0xC082.0100 LSI_1: Enable Image, VAS=A32, VDW=D32, LAS=Mem. Space,
PGM=data, SUPER=non-priv, Posted Write enabled, BLT allowed.
D:0x0000.0040 to A:0x00012C 0x4000.0000 LSI_2: Base Address set to 0x4000.0000
D:0x0000.0060 to A:0x000130 0x6000.0000 LSI_2: Bound Address set to 0x6000.0000
D:0x0000.00C0 to A:0x000134 0xC000.0000 LSI_2: Translation Offset set to 0xC000.0000
D:0x0001.C2C0 to A:0x000128 0xC0C2.0100 LSI_2: Enable Image, VAS=A32, VDW=D64, LAS=Mem. Space,
PGM=data, SUPER=non-priv, Posted Write enabled, BLT allowed.