User guide
27
Issued June 20, 2007
M5000 Series: User Guide
AMCC 440GX PowerPC Embedded Processor
3.2 AMCC 440GX PowerPC Embedded Processor
Designed specifically to address high-end embedded applications, the PowerPC 440GX
(PPC440GX) provides a high-performance, low power solution that interfaces to a wide range of
peripherals by incorporating on-chip power management features and lower power dissipation.
This chip contains a high-performance RISC processor core, DDR SDRAM controller, PCI-X bus
interface, Ethernet interface, controls for external ROM and peripherals, DMA with scatter-gather
support, serial ports, IIC interface, and general purpose I/O.
For more detailed information about the PowerPC 440GX, please refer to the PowerPC 440GX
Embedded Processor Data Sheet and the PowerPC 440GX Embedded Processor User's Manual.
Processor DDR-SDRAM Memory
The amount of DDR SDRAM memory used is 256MiB, using 512Mb chips running at 166 MHz.
• Four 2-byte wide memory chips are used as the data memory banks.
• One 2-byte wide memory chip is used as the parity bank (only 8 data lines are used by the
processor).
All the memory chips are 8 or 16MiB x 16 bits x 4 banks.
UART and Serial Lines
The IBM440GX PowerPC processor includes two universal asynchronous receiver/transmitters
(UART).
The two UART I/O pins are connected to a multi-protocol transceiver which can handle 2Tx/2Rx
RS-232 interfaces, or one RS232 interface and a single RS-485/422 transceiver simultaneously.
The three serial lines are available on the serial front panel connector but only two of them can be
used simultaneously. The first UART is always used for one RS-232 line while the second UART is
configurable.
Ethernet Interfaces
All four processor Ethernet interfaces are connected:
• The first two Ethernet interfaces (10/100-TX) are connected to the Fast Ethernet Transceiver.
The first Ethernet link is connected to the on-board RJ45 copper connector and the second is
routed to the I/O Spacer.
• The second two Ethernet interfaces (10/100/1000Mbps) are connected to the I/O Spacer They
are configured as Reduced Gigabit Media Independent Interfaces (RGMII)