User guide

32
M5000 Series: User Guide
Issued June 20, 2007
Processor Subsystem
3.4 PCI-X to PCI-X Bridges
The PLX6540 64-bit PCI-X to PCI-X bridge is designed for high performance, high availability
applications, in PCI-X to PCI conversion, bus expansions, frequency conversions from faster PCI-
X to slower PCI-X or from slower PCI-X to faster PCI-X bus, address remapping, high availability
hot swap and universal system-to-system bridging. PCI6540 has sophisticated buffer management
and buffer configuration options designed to provide customizable performance for very efficient
PCIX-PCI conversion and processor bridging. PCI6540 allows up to 2KiB prefetch during read and
timed FIFO flush management.
Power-up / Reset Configuration Options
Many options of the PCI6540 can be configured at power-up or reset. Because most of the options
can be modified using software, only a few options are connected to dip-switches.
Application Modes
Non-universal transparent and non-universal non-transparent modes are the only supported modes .
The transparent mode is the default mode. A dip-switch is used to select between transparent and
non-transparent mode.
In non-transparent mode you can choose which port has boot priority using a dip-switch (controls
P_BOOT signal). P_BOOT is deasserted when board configuration is initiated from the VME side
(non-transparent mode is selected).See “PCI-X to PCI-X Bridges SW2, SW9, SW8 settings” on
page 14.
EEPROM
At boot-up, an external EEPROM can be used by the PCI6540 to initialize its internal registers. The
EEPROM auto-load process is only initiated when the primary reset input is deasserted. Data is
always downloaded from address 0. Hosts accesses are only allowed when the download process is
completed (bit EEPAUTO status is 0).
A dip-switch is used to control the use of the EEPROM at start-up.
See “PCI-X to PCI-X Bridges SW2, SW9, SW8 settings” on page 14.
Secondary Port Arbiter Setup
As the only built-in arbiter present on the secondary PCI bus, the PCI6540 internal arbiter is used to
arbitrate.
Primary Interface
The primary interface of this bridge is connected to the Primary PCI Segment and is 64-bit 133MHz
PCI-X only.