User guide

65
Issued June 20, 2007
M5000 Series: User Guide
Reset Network
7.2 Reset Network
The board reset network is centralized around the reset PLD. Output reset signals are routed first to
the reset PLD before being propagated to the other board components.
The primary sources of reset are the power-up reset controller and reset button. Other sources are
various software resets from the processor, PCI-X to PCI-X bridges, VME reset, RACEway reset
and PMC modules etc.
The following devices are considered as possible reset sources:
• 2 PPMC sites
• TUNDRA Universe II VME-to-PCI bridge
• MERCURY PXB++ Race++-to-PCI Bridge
• 3 PCI6540 PCIX-to-PCIX bridges
• AMCC 440GX PowerPC processor
• Power cycle (cold boot)
• On-board reset button (warm boot)
Any kind of reset (or power up) is forwarded to the CPLD which ensures that all the components
are reset correctly (without any reset loop).
• The CPLD is always the first component to receive the initial reset signal.
• The CPLD transmits the reset to the Universe.
• The CPLD resets all the other components on the board