User guide

76
M5000 Series: User Guide
Issued June 20, 2007
PLD Registers
PCI_CFG
7 PMC2_PCIX PMC#2 PCI(-X) Bus Mode (Read-Only): set to 1 if PCI-X mode detected on
PCI(-X) bus where PMC site #2 is located, 0 otherwise
6 PMC1_PCIX PMC#1 PCI(-X) Bus Mode (Read-Only): set to 1 if PCI-X mode detected on
PCI(-X) bus where PMC site #1 is located, 0 otherwise
5 PMC2_CLK1 PMC#2 PCI(-X) Bus Clock Speed Bit 1 (Read-Only): set to 1 if clock speed
detected on PCI(-X) bus where PMC site #2 is located is over 66MHz, 0
otherwise
4 PMC2_CLK0 PMC#2 PCI(-X) Bus Clock Speed Bit 0 (Read-Only): set to 1 if clock speed
detected on PCI(-X) bus where PMC site #2 is located is 66MHz or 133MHz, 0
otherwise (33MHz or 100MHz)
3 PMC1_CLK1 PMC#1 PCI(-X) Bus Clock Speed Bit 1 (Read-Only): set to 1 if clock speed
detected on PCI(-X) bus where PMC site #1 is located is over 66MHz, 0
otherwise
2 PMC1_CLK0 PMC#1 PCI(-X) Bus Clock Speed Bit 0 (Read-Only): set to 1 if clock speed
detected on PCI(-X) bus where PMC site #1 is located is 66MHz or 133MHz, 0
otherwise (33MHz or 100MHz)
1 P_CLK1 Processor PCI-X Bus Clock Speed Bit 1 (Read-Only): set to 1 if clock speed
detected on PCI-X bus where processor is located is over 66MHz, 0 otherwise
0 P_CLK0 Processor PCI-X Clock Speed Bit 0 (Read-Only): set to 1 if clock speed detected
on PCI-X bus where processor is located is 66MHz or 133MHz, 0 otherwise
(33MHz or 100MHz)
TABLE A-2. Clock speed display
PCIX CLK1 CLK0 PCI-X Mode
000PCI 33 MHz
001PCI 66 MHz
101PCI-X 66 MHz
110PCI-X 100 MHz
111PCI-X 133 MHz