User guide

81
Issued June 20, 2007
M5000 Series: User Guide
VMEbus Slave Images
B-2 VMEbus Slave Images
PCI Master Enable
In addition to the configuration registers for the VMEbus slave images, one control register bit is
essential for mapping VMEbus cycles to PCI bus cycles through the Universe IID. The PCI master
enable ('BM') bit located in the PCI_CSR register space (offset: 0x004). This bit is set as default
after power up.
Some VMEbus Slave Image examples are shown in Figure B-1.
FIGURE B-1.
Configuration
example for
VMEbus slave
images
PCI busVMEbus
VME Slave Image
# 0
VMEbus A16, supervisor
AM codes
0x4FFF
0x0000
UNIVERSE IID
PCI bus Config. Space
VME Slave Image
# 1
VMEbus A24, all AM
codes, No write-posting or
read prefetching. PCI
Lock of VMEbus RMW
enabled.
0x3FFFFF
0x100000
0x023FFFFF
0x02100000
PCI bus I/O Space.
VME Slave Image
# 3 (not used)
VME Slave Image
# 2
VMEbus A32, all AM
codes, Write-posting and
read prefetching enabled.
0x7FFF.FFFF
0x4000.0000
0x9FFF.FFFF
0x6000.0000
PCI bus Memory Space.
VME Register
Access Image
VMEbus A24, all AM
codes
0x000FFF
0x000000