Matrox Solios Installation and Hardware Reference Manual no.
Matrox® is a registered trademark of Matrox Electronic Systems Ltd. Microsoft® and Windows®, are registered trademarks of Microsoft Corporation. Intel® is a registered trademark of Intel Corporation. Altera®, Stratix®, and Quartus® are registered trademarks of Altera Corporation. In addition, Altera Byteblaster™ is a trademark of Altera Corporation. Camera Link® is a registered trademark of the Automated Imaging Association (AIA). PCI-X® and PCI Express® are registered trademarks of PCI-SIG.
Contents Chapter 1: Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Matrox Solios boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Acquisition with Matrox Solios eCL/XCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Acquisition with Matrox Solios eA/XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Processing capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 3: Using multiple Matrox Solios boards . . . . . . . . . . . . 39 Multiple board installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Simultaneous image capture from different boards . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Chapter 4: Matrox Solios hardware reference . . . . . . . . . . . . . . 43 Matrox Solios hardware reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Acquisition path . . . .
Processing FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Possible processing operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Processing FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 High-speed serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 PCI-X interface . . . . . . . . . . . . . . . . . . . . . . . . .
Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards 120 Camera Link video input connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 External auxiliary I/O connector 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 External auxiliary I/O connector 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Internal auxiliary I/O connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 JTAG connector .
Chapter 1 Chapter 1: Introduction This chapter briefly describes the features of the Matrox Solios boards, as well as the software that can be used with the boards.
Chapter 1: Introduction Matrox Solios boards The Matrox Solios family consists of five members: two PCI-X compliant, single-slot frame grabbers, and three PCIe compliant, single-slot frame grabbers. If purchased with the optional Processing FPGA, members also have custom image processing capabilities. The PCI-X compliant boards are Matrox Solios XCL and Matrox Solios XA. The PCIe compliant boards are Matrox Solios eCL and Matrox Solios eA.
Matrox Solios boards 9 Matrox Solios eCL/XCL-B Matrox Solios eCL/XCL-B supports acquisition from one Camera Link device in the Base configuration; the device can be a power-over Camera Link (PoCL) video source. Matrox Solios eCL/XCL-B supports Camera Link frequencies of up to 85 MHz. Unlike the other Matrox Solios eCL/XCL boards, Matrox Solios eCL/XCL-B does not support the Processing FPGA option.
Chapter 1: Introduction Matrox Solios eCL/XCL dual-Base/single-Medium When in dual-Base mode, Matrox Solios eCL/XCL dual-Base/single-Medium supports acquisition from up to two Camera Link devices in the Base configuration. When in single-Medium mode, the board supports one Camera Link device in the Medium configuration. Matrox Solios eCL/XCL dual-Base/single-Medium boards are available in two maximum frequencies. By default, the boards support Camera Link frequencies of up to 66 MHz.
Matrox Solios boards Matrox Solios eCL/XCL dual-Base/single-Medium (single-Medium mode) Acquisition memory (64/128/256 MB) 64 DDR (up to 1.6 GB/s)*** First MDR-26 connector Clock Data (24) & Syncs (4)* ChannelLink Receiver #2 24 24 Data (24) & Syncs (4)* Clock ChannelLink Receiver #1 Cam Ctrl (4) LVDS drivers SerTFG SerTC LVDS driver & receiver Demultiplexer Second MDR-26 connector 64 (up to 1.
Chapter 1: Introduction Matrox Solios eCL/XCL-F Matrox Solios eCL/XCL-F supports acquisition from one Camera Link device in the Base, Medium, or Full configuration (with up to 10 taps). Matrox Solios eCL/XCL-F supports Camera Link frequencies of up to 85 MHz; additionally, Matrox Solios eCL/XCL-F supports the Processing FPGA option.
Matrox Solios boards 13 Acquisition with Matrox Solios eA/XA Matrox Solios eA/XA boards are high-performance, high-frequency, and high-fidelity analog frame grabbers. They are available in three factory-configured versions: Matrox Solios eA/XA Single, Matrox Solios eA/XA Dual, and Matrox Solios eA/XA Quad. Matrox Solios eA/XA Single Matrox Solios eA/XA Single can acquire from one analog video source.
Chapter 1: Introduction Matrox Solios eA/XA Dual Matrox Solios eA/XA Dual can acquire from up to two independent analog video sources. For added flexibility, each acquisition path has an input selector that can switch between receiving input from one of two video sources. Matrox Solios eA/XA Dual supports the optional Processing FPGA.
Matrox Solios boards 15 Acquisition with Matrox Solios eA/XA Quad Matrox Solios eA/XA Quad can acquire from up to four independent analog video sources. For added flexibility, each acquisition path has an input selector that can switch between receiving input from one of two video sources. This means, for example, that you can connect two 4-tap video sources to the eA/XA Quad board and switch between them. Matrox Solios eA/XA Quad supports the optional Processing FPGA.
Chapter 1: Introduction Processing capabilities To reduce the number of image processing tasks performed by the CPU of the host computer (Host), most Matrox Solios boards (except for those mentioned earlier) can be purchased with the optional Processing FPGA. Using this FPGA, Matrox Solios can process and format image data. Processing FPGA The Processing FPGA is a highly customizable processing core, based on the Altera Stratix family of pin-compatible FPGA devices.
Matrox Solios boards 17 • Auxiliary, multi-purpose signals. These are non-video signals that can support one or more functionalities depending on the auxiliary signal (for example, trigger input or timer output). The number of signals each board supports is given in the table below.
Chapter 1: Introduction Data transfer Under optimum conditions, Matrox Solios can exchange data with the Host at a peak transfer rate of up to 1 Gbyte/sec. For Matrox Solios XCL and XA, these conditions include using the board in a 133 MHz PCI-X slot. For Matrox Solios eCL and eA, these conditions include using the board in a x4 or x8 PCIe slot with at least 4 active lanes; the eCL-B and eA Single boards can use a x1 PCIe slot. If Matrox Solios XCL and XA are used with a conventional 3.
Software 19 Software To operate Matrox Solios, you can use one or more Matrox Imaging software products that supports the board. These are the Matrox Imaging Library (MIL) and its derivatives (MIL-Lite, Matrox Inspector, and Matrox Intellicam). All Matrox software is supported under Windows; consult your software manual for supported Windows environments.
Chapter 1: Introduction Essentials to get started To begin using Matrox Solios, you must have a computer with the following: • An available conventional PCIe, PCI, or PCI-X slot. ❖ Note that only Matrox Solios eCL and eA support a PCIe slot, and it should be a x4 or x8 PCIe slot. For Matrox Solios eCL-B or eA Single, it can also be a x1 slot. • Processor with an Intel 32-bit architecture (IA32) or equivalent. • A relatively up-to-date PCIe/PCI/PCI-X chipset.
Inspecting the Matrox Solios package 21 Inspecting the Matrox Solios package You should check the contents of your Matrox Solios package when you first open it. If something is missing or damaged, contact your Matrox representative. Standard items With all Matrox Solios packages You should receive the following item: • The Matrox Solios eCL, XCL, eA, or XA board, depending on which was purchased.
Chapter 1: Introduction on the video data (sync on green). Otherwise, you must use the Matrox DVI-TO-8BNC/O cable or a custom cable that re-routes the synchronization signals to the appropriate pins. ❖ If needed, you can purchase a Camera Link or PoCL Camera Link cable from the video source manufacturer, 3M Interconnect Solutions for Factory Automation, Intercon 1, or other third parties.
Installation 23 For in-depth hardware information, refer to Chapter 4: Matrox Solios hardware reference; whereas for a summary of this information, as well as environmental and electrical specifications, and connector pinout descriptions, see Appendix B: Technical information. This manual occasionally makes reference to a MIL-Lite function. However, anything that can be accomplished with MIL-Lite can also be accomplished with MIL or Matrox Inspector.
Chapter 1: Introduction
Chapter 2 Chapter 2: Hardware installation This chapter explains how to install your Matrox Solios board in your computer.
Chapter 2: Hardware installation Installing your Matrox Solios board Before you install your Matrox Solios board, some precautionary measures must be taken. Turn off the power to your computer and its peripherals, and drain static electricity from your body (by touching a metal part of the computer chassis). Proceed with the following steps to install your board. Note that your board should be installed before you install your software. 1.
Installing your Matrox Solios board Important 27 Some computers have a large, black-ridged heat sink that prevents long boards from using some of the PCI board slots. Matrox Solios must not touch the heat sink. Therefore, choose a slot where the board completely avoids it. If you cannot find a suitable slot, contact your computer dealer. If you also need to install the adapter board/bracket of your Matrox Solios board, you need an additional slot.
Chapter 2: Hardware installation 4. Position your Matrox Solios board in the selected slot, and then press the board firmly but carefully into the connector of the slot. When installing Matrox Solios XCL or XA in a conventional 32-bit slot, only the 32-bit portion of the edge connector is connected in the slot. The other portion will remain out. Important When installing a Matrox Solios eCL or eA board in a x16 PCIe slot, special care must be taken to avoid damaging the board.
Installing your Matrox Solios board 29 5. Anchor the board using the screw that you removed in step 3. 6. If required, install the adapter board/bracket of your Matrox Solios board, as described in the section Installing an adapter board/bracket, later in this chapter. 7. Attach your video sources, as described in the section Connecting video sources, later in this chapter. 8. Turn on your computer.
Chapter 2: Hardware installation Installing an adapter board/bracket To install the adapter board/bracket of Matrox Solios eCL/XCL or eA/XA, proceed with the following steps. 1. Make sure that your Matrox Solios eCL/XCL or eA/XA board is fastened to the computer chassis. 2. If you are installing the adapter board of Matrox Solios eA/XA and the slot that you have selected for the board is not a PCI/PCI-X slot, break off the board’s tab if it interferes with other components in the computer.
Installing an adapter board/bracket 31 Matrox Solios board and the cable in this position, only the connector on one end of the cable will latch properly onto the internal auxiliary I/O connector. The other end will not and excessive force might damage the cable connector. In addition, you should hear a snap when the hooks of the cable’s connector latch onto the internal auxiliary I/O connector. 4.
Chapter 2: Hardware installation 5. If you are installing the adapter board of Matrox Solios eA/XA in a PCI/PCI-X/PCIe slot, align the board’s tab with the slot’s connector, and then press the board firmly but carefully into the slot’s connector. For other types of slots or when installing the adapter board of Matrox Solios eCL/XCL, slide the bracket into the opening at the back of the selected slot. 6. Anchor the bracket to the chassis using the screw that you removed in the previous section.
Connecting video sources 33 Connecting video sources Connecting to Matrox Solios eCL/XCL-B The Matrox Solios eCL/XCL-B board has the following connectors on its bracket: • One Camera Link-compliant video input connector. Used to receive video input, timing, and synchronization signals and transmit/receive communication signals between the video source and the frame grabber. • External I/O connector 0 (DBHD-15 or DB-9).
Chapter 2: Hardware installation Connecting to Matrox Solios eCL/XCL dual-Base/single-Medium or eCL/XCL-F boards Matrox Solios eCL/XCL dual-Base/single-Medium and Matrox Solios eCL/XCL-F boards have the following connectors: • Two Camera Link-compliant video input connectors (on the bracket). Used to receive video input, timing, and synchronization signals and transmit/receive communication signals between the video source and the frame grabber. • Internal auxiliary I/O connector (50-pin).
Connecting video sources 35 One video source can be connected to each Camera Link connector (dual-Base mode) or a single video source can be connected to both connectors (single-Medium and single-Full modes). Use standard Camera Link cables. You can purchase such a cable from your video source manufacturer, 3M Interconnect Solutions for Factory Automation, Intercon 1, or other third parties. Note that this cable is not available from Matrox.
Chapter 2: Hardware installation • External auxiliary I/O connector 1 (DB-9). Used to receive opto-isolated trigger input signals. Analog Video Input Connector #1 Connector #0 External Auxiliary I/O Connector #0 Connector #1 You can use the Matrox DVI-TO-8BNC/O input cable to connect to your video sources.
Connecting video sources 37 Connect the cable’s DVI connector to one of the DVI connectors on Matrox Solios eA/XA. Then, connect the BNC connectors as follows. BNC label* ,† Signal on DVI connector 0 Signal on DVI connector 1 Expected input, with respect to the DVI connector. VID IN 0 P0_VID_IN_A P0_VID_IN_B Video input A or B for path 0 (monochrome or red input). VID IN 1 P1_VID_IN_A P1_VID_IN_B Video input A or B for path 1 (monochrome or green input).
Chapter 2: Hardware installation
Chapter 3 Chapter 3: Using multiple Matrox Solios boards This chapter explains how to use multiple Matrox Solios boards.
Chapter 3: Using multiple Matrox Solios boards Multiple board installation You can install and use multiple Matrox Solios boards in one computer. To use multiple Matrox Solios boards, install each additional Matrox Solios board as you installed the first board (refer to Chapter 2: Hardware installation).
Simultaneous image capture from different boards 41 The use of a high performance PCIe/PCI/PCI-X core-logic chipset is necessary to sustain PCIe/PCI/PCI-X transfers to Host memory. If a high performance chipset and a 133 MHz 64-bit PCI-X slot is used with Matrox Solios XCL and XA, you should not have a problem with dropped frames. The list of platforms that are known to be compatible with Matrox Solios are available on the Matrox web site, under the board’s compatibility list.
Chapter 3: Using multiple Matrox Solios boards
Chapter 4 Chapter 4: Matrox Solios hardware reference This chapter explains the architecture, features, and modes of the Matrox Solios eCL/XCL and Matrox Solios eA/XA hardware.
Chapter 4: Matrox Solios hardware reference Matrox Solios hardware reference This chapter provides information on the Matrox Solios eCL/XCL and Matrox Solios eA/XA hardware. It covers the architecture, features, and modes of their acquisition section. In addition, it covers the Matrox Solios hardware related to the processing and transfer of data.
Matrox Solios hardware reference 45 Acquisition path This manual uses the term acquisition path to refer to a path that has the components to, for example, digitize or capture a video input signal. The term independent acquisition path is used to refer to an acquisition path that can, if required, acquire data from an input source independently from another such path on the same frame grabber.
Chapter 4: Matrox Solios hardware reference Matrox Solios eCL/XCL acquisition section Matrox Solios eCL/XCL can capture video from digital video sources compliant with the Camera Link specification. Matrox Solios eCL/XCL supports monochrome and component RGB acquisition. Besides standard Camera Link video sources, it also supports additional types of video sources, including time-multiplexed video sources.
Matrox Solios eCL/XCL acquisition section 47 Performance The video timing parameters supported by the board are as follows: Maximum Number of pixels / line (including sync and blanking) 64 K Number of lines / frame (including sync and blanking) 64 K Pixel clock eCL/XCL-B 85 Mhz eCL/XCL dual-Base/single-Medium without fast Camera Link option 66 Mhz eCL/XCL dual-Base/single-Medium with fast Camera Link option 85 Mhz eCL/XCL-F 85 Mhz Bandwidth eCL/XCL-B 255 Mbytes/sec eCL/XCL dual-Base/single-
Chapter 4: Matrox Solios hardware reference The video sources can be frame, field, or line-scan video sources. Note that the acquisition paths in dual-Base mode are completely independent, and therefore the video sources do not need to be identical when running in dual-Base mode.
Matrox Solios eCL/XCL acquisition section 49 UART SerTFG SerTC Clock ChannelLink Receiver #2 24 24 Data (24) & Syncs (4)* Clock ChannelLink Receiver #1 Cam Ctrl (4) LVDS drivers SerTFG SerTC PSG #1 LVDS drivers Cam Ctrl (4) Data (24) & Syncs (4)* First MDR-26 connector LVDS driver & receiver LVDS driver & receiver Demultiplexer Demultiplexer Second MDR-26 connector 32 LUTs Video to PCI-X Bridge 32 LUTs PSG #0 UART HSYNC Out (2) VSYNC Out (2) Clock Out (2) DBHD-44 and DB-9 connector
Chapter 4: Matrox Solios hardware reference First MDR-26 connector Clock Data (24) & Syncs (4)* ChannelLink Receiver #2 24 Data (24) & Syncs (4)* Clock ChannelLink Receiver #1 Cam Ctrl (4) LVDS drivers SerTFG SerTC 24 LVDS driver & receiver Demultiplexer Second MDR-26 connector 48 LUTs Video to PCI-X bridge PSG UART DBHD-44 and DB-9 connectors** HSYNC Out (1) VSYNC Out (1) Clock Out (1) Aux In (4) Aux Out (2) LVDS drivers and receivers Aux I/Os (4) TTL buffers OptoAux (4) Optocou
Matrox Solios eCL/XCL acquisition section Clock Data (28)* First MDR-26 connector Clock Data (28)* ChannelLink Receiver #2 Data (24) & Syncs (4)* Clock ChannelLink Receiver #1 Cam Ctrl (4) LVDS drivers SerTFG SerTC 28 28 24 LVDS driver & receiver Demultiplexer Second MDR-26 connector ChannelLink Receiver #3 51 64 LUTs Video to PCI-X bridge PSG UART DBHD-44 and DB-9 connectors** HSYNC Out (1) VSYNC Out (1) Clock Out (1) Aux In (4) Aux Out (2) LVDS drivers and receivers Aux I/Os (4)
Chapter 4: Matrox Solios hardware reference Supported video sources Each acquisition path supports the following video sources: Video sources supported per acquisition path Camera Link Standard • One tap x 8/10/12/14/16-bit. • Two tap x 8/10/12-bit. • One 3 x 8-bit (RGB). Not Camera Link Standard • Two tap 14/16-bit with time-multiplexing. • Four tap x 10/12-bit with time-multiplexing. • Four tap 8-bit with time-multiplexing.
Matrox Solios eCL/XCL acquisition section 53 write to four. This means that using Matrox Solios eCL/XCL-F, for example, you could only grab from an 8-tap x 8-bit video source if four of the taps carry pixels that are sequential to the other four taps. To establish the number of non-sequential memory regions to which your video source must write, refer to the documentation accompanying your video source.
Chapter 4: Matrox Solios hardware reference Demultiplexers Each acquisition path of the board features a demultiplexer. It can deserialize input from time-multiplexed video sources on a clock basis; time-multiplexed video sources can output twice the amount of data as is possible when using other video sources with the same amount of cabling. When enabled, the demultiplexer assumes that two video streams share the same data path and that the streams are interleaved based on the clock cycle.
Matrox Solios eCL/XCL acquisition section 55 Dual-Base/single-Medium and single-Full boards Matrox Solios eCL/XCL dual-Base/single-Medium and Matrox Solios eCL/XCL-F boards each have programmable LUTs. In dual-Base mode, the LUTs can be operated in the following configurations per acquisition path*: • 8 palettes of one, two, three, or four 256-entry 8-bit LUTs. • 4 palettes of one or two 1024-entry 8- or 16-bit LUTs. • 1 palette of one or two 4096-entry 8- or 16-bit LUTs.
Chapter 4: Matrox Solios hardware reference UARTs Matrox Solios eCL/XCL-B and Matrox Solios eCL/XCL-F each offer a single LVDS-compatible Matrox serial interface. Matrox Solios eCL/XCL dual-Base/single-Medium offers two LVDS-compatible serial interfaces; however, when operating in single-Medium mode, only one LVDS compatible serial interface can be used. Each interface is mapped as a COM port so that it can be accessed through the Win32 API.
Matrox Solios eCL/XCL acquisition section 57 Matrox Solios eCL/XCL-B The following tables summarize the synchronization, timing, and control signals supported by Matrox Solios eCL/XCL-B. For example, P0_TTL_AUX_IO_0 can be defined as a timer output (M_TIMER3 on M_DEV0), trigger input (trigger controller 0 on acq path 0), field polarity input, user input, or user output (M_USER_BIT2) signal. CL connect. stands for Camera Link connector. TTL aux. I/O* LVDS cam.
Frame valid input 1 VSYNC output 1 Line valid input 1 HSYNC output 1 Data valid input 1 Clock input 1 Clock output 1 LVDS cam. ctrl CC4 CC3 CC2 CL connect. CC1 Type of signal Max # signals* 58 Chapter 4: Matrox Solios hardware reference Received with data LVDS dedicated signals† CL connect. 0 0 0 0 0 0 0 0 0 0 0 Xclk (CL connect.) 0 0 0 0 *. The maximum # for each signal type cannot always be attained.
Matrox Solios eCL/XCL acquisition section 59 The following table lists the auxiliary input signals (or auxiliary I/O signals set to input) that can be rerouted onto output signals and the output signals onto which they can be rerouted. TTL aux. I/O LVDS cam. ctrl LVDS aux.
Chapter 4: Matrox Solios hardware reference TTL aux. I/O* LVDS cam.
Matrox Solios eCL/XCL acquisition section 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 HSYNC output Data valid input Clock input Clock output LVDS dedicated signals† ‡ CL connect. 1 1 0 CL connect. 0 1 Line valid input CC4 1 CC3 0 VSYNC output CC2 1 Received with data CL connect. 1 CC1 1 CC4 1 CC3 0 CC2 Max # signals* Frame valid input CL connect. 0 CC1 Type of signal Acquisition path LVDS cam.
Chapter 4: Matrox Solios hardware reference The following table lists the auxiliary input signals (or auxiliary I/O signals set to input) that can be re-routed onto output signals and the output signals onto which they can be re-routed. TTL aux. I/O* LVDS cam.
Matrox Solios eCL/XCL acquisition section 63 Auxiliary signals and camera control signals Matrox Solios eCL/XCL supports multi-purpose auxiliary input and output signals. Auxiliary signals are non-video signals that can be controlled and support one or more functionalities depending on the auxiliary signal (for example, as trigger input or timer output signals).
Chapter 4: Matrox Solios hardware reference Matrox Solios eCL/XCL dual-Base/single-Medium in dual-Base mode has auxiliary/camera control signals in the following formats: Auxiliary signals # per path # total LVDS camera control output signals. 4 8 TTL auxiliary input or output signals. 2 (+2 depending on type of signal) 6 Opto-isolated auxiliary input signals. depends on type (2 reserved for P0, 2 not specified) 4 LVDS auxiliary input signals.
Matrox Solios eCL/XCL acquisition section 65 Timers Each PSG has four timers*. These timers can each generate a timer output signal with up to two pulses; timer output signals can be used to control the exposure time and other external events related to the video source (such as a strobe). The timer output signals can be output using camera control signals or auxiliary output signals (or auxiliary I/O signals in output mode).
Chapter 4: Matrox Solios hardware reference Trigger The board accepts trigger input signals which allow, for example, image acquisition to be synchronized with external events. Each PSG has 4 trigger controllers.
Matrox Solios eCL/XCL acquisition section 67 The opto-isolated trigger signals pass through an opto-coupler. The voltage difference across the positive and negative components of the signal must be between 4.06 V and 9.165 V for logic high, and between -5.0 V and 0.8 V for logic low. Synchronization For each PSG, the board can supply one horizontal (HSYNC) and one vertical (VSYNC) synchronization signal to the video source.
Chapter 4: Matrox Solios hardware reference increments the counter; the reverse Gray code sequence will then represent the backward direction and decrement the counter. You can specify the direction of movement occurring when the Gray code sequence is 00 - 01 - 11 - 10, using MdigControl() with M_ROTARY_ENCODER_DIRECTION. The rotary decoder supports a maximum encoder frequency equal to the pixel clock frequency of the video source.
Matrox Solios eCL/XCL acquisition section 69 You can specify the on/off state of a required output signal and have the PSG generate and route it to an auxiliary output signal (or auxiliary I/O signals in output mode) configured as a user signal; your application can set the on/off state of the signal based on some analysis.
Chapter 4: Matrox Solios hardware reference Matrox Solios eA/XA acquisition section Matrox Solios eA/XA is available in three versions: Matrox Solios eA/XA Quad, Matrox Solios eA/XA Dual, and Matrox Solios eA/XA Single. eA/XA Quad has four completely independent acquisition paths, allowing simultaneous acquisition from four independent video sources. eA/XA Dual has two independent acquisition paths; eA/XA Single, on the other hand, has one acquisition path.
Matrox Solios eA/XA acquisition section The following image is the acquisition section of Matrox Solios eA/XA.
Chapter 4: Matrox Solios hardware reference Performance The video timing parameters supported by the board are as follows: Maximum Number of pixels / line (including sync and blanking) 64 K Number of lines / frame (including sync and blanking) 64 K Pixel clock for single sampling rate operation 65 MHz Bandwidth eA/XA Single 130 Mbytes/sec eA/XA Dual 260 Mbytes/sec eA/XA Quad 520 Mbytes/sec Analog bandwidth (-3 db cutoff frequency) 100 MHz Analog input Matrox Solios eA/XA includes the ele
Matrox Solios eA/XA acquisition section 73 Input voltage level and protection The various amplification stages on Matrox Solios eA/XA are able to provide a maximum peak signal of 2.4 V without saturation. Any positive video signal level greater than this threshold will be distorted, so it is not recommended to feed a signal above 3 V with termination (6 V unterminated). Clamping diodes protect video inputs from overvoltage. The diodes clamp (clip) the inputs if they go under -5 V or above +5 V.
Chapter 4: Matrox Solios hardware reference Adjusting the reference levels For each acquisition path, you can adjust the signal’s black and white reference levels so that the full dynamic range of each 10-bit A/D is used. Matrox Solios eA/XA uses the offset-gain topology to adjust the black and white reference levels of the signal. The topology uses a variable offset controller followed by a variable gain controller; the signal can be routed through a 2:1 attenuator before being restored and offset.
Matrox Solios eA/XA acquisition section 75 There are three ways to program the reference levels and the attenuator. You can specify the actual black and white voltage levels of your input signal and have the software calculate appropriate values for each element in the offset-gain topology. You can have the software emulate an A/D with programmable black and white references and specify the levels as a percentage of their possible values.
Chapter 4: Matrox Solios hardware reference UARTs Matrox Solios eA/XA Quad offers four RS-232 compatible serial interfaces, Matrox Solios eA/XA Dual offers two, whereas Matrox Solios eA/XA Single offers one. Each interface is mapped as a COM port so that it can be accessed through the Win32 API. Each interface is comprised of both a transmit port and a receive port, permitting the interface to work in full-duplex (bidirectional) mode. The interfaces are on the DVI connectors.
Matrox Solios eA/XA acquisition section 77 PSGs Matrox Solios eA/XA Quad features four programmable synchronization generators (PSGs), Matrox Solios eA/XA Dual features two, whereas Matrox Solios eA/XA Single features one. The PSGs are responsible for managing all input and output video timing, synchronization, trigger, timer, and user signals. The PSGs on Matrox Solios eA/XA allow the board to adapt to many video standards. Each PSG allows for independent acquisition from a video source.
Chapter 4: Matrox Solios hardware reference Synchronization, timing, and control signals The following tables summarize the synchronization, timing, and control signals supported by Matrox Solios eA/XA. Most of these signals are available by defining an auxiliary (multi-purpose) signal as the required synchronization, timing, or control signal. For example, P0_TTL_AUX(TRIG)_IN can be defined for acquisition path 0 as a trigger input (trigger controller 0), field polarity input, and user input signal.
Matrox Solios eA/XA acquisition section 0 T0 1 T1 T0 2 3 Field polarity input 0 1 2 3 Data valid input 3 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 3 0 0 0 1 0 2 0 3 3 3 T1 T2 T3 T2 T3 T2 T3 T2 T3 0 0 User output 0 (bit of static-user-output 1 register M_USER_BITn**) 2 2 T2 T3 T2 T3 T2 T3 T2 T3 2 Timer-clock input 2 T2 T3 T2 T3 T2 T3 T2 T3 T1 T0 1 T2 T3 T2 T3 T2 T3 T2 T3 T1 T0 1 P3_LVDS/TTL_AUX_OUT1 P3_OPTO_AUX(TRIG)_IN Trigger controller affected by input signal 0
Chapter 4: Matrox Solios hardware reference 3 1 in + 1 out P3_LVDS_TTL_VSYNC_IO CSYNC or 0 1 in + 1 out P0_LVDS/TTL_CHSYNC_IO HSYNC** 1 1 in + 1 out P1_LVDS/TTL_CHSYNC_IO 2 1 in + 1 out P2_LVDS/TTL_CHSYNC_IO Clock 3 1 in + 1 out P3_LVDS/TTL_CHSYNC_IO 0 1 in/out P0_LVDS/TTL_CLK_IO 1 1 in/out P1_LVDS/TTL_CLK_IO 2 1 in/out P2_LVDS/TTL_CLK_IO 3 1 in/out P3_LVDS/TTL_CLK_IO P3_LVDS/TTL_AUX_OUT1 P3_LVDS/TTL_AUX_OUT0 P2_LVDS/TTL_AUX_OUT1 P2_LVDS/TTL_AUX_OUT0 P2_LVDS_TTL_VSYNC_I
Matrox Solios eA/XA acquisition section 81 Auxiliary signals Matrox Solios eA/XA supports multi-purpose auxiliary input and output signals. Auxiliary signals are non-video signals that can be controlled and support one or more functionalities depending on the auxiliary signal (for example, as trigger input or timer output signals). The table in the previous subsection identifies the functions to which an auxiliary signal can be defined. You specify their function in the DCF file.
Chapter 4: Matrox Solios hardware reference With interlaced video sources, you can typically establish which field is being input by noting the phase shift between the horizontal and the vertical synchronization signals. Alternatively, you can define an auxiliary signal as a field polarity input signal and transmit the field polarity on this signal.
Matrox Solios eA/XA acquisition section 83 • A clock based on another timer output of the same PSG. • A clock based on an external pixel clock signal. • A clock based on the HSYNC or VSYNC signal generated by the PSG. To set up a timer, use the MIL-Lite function MdigControl() with M_TIMER... Set the clock source of a timer using MdigControl() with M_TIMER_CLOCK_SOURCE. To transmit the output of a timer, use MdigControl() with M_IO_SOURCE* + M_AUX_IOn set to M_TIMERm.
Chapter 4: Matrox Solios hardware reference User signals Auxiliary signals can be used for application-specific user input and output. Any auxiliary output signal (or I/O signal set to output) can be configured as a user output signal to start or stop an external event. In this case, the state (on/off ) of a bit in a user settable register (static-user-output register) is routed onto its associated auxiliary output signal. This bit is referred to as a user-bit.
Processing FPGA 85 Processing FPGA To reduce the number of image processing tasks the Host CPU has to do, most Matrox Solios boards can be purchased with the optional Processing FPGA. This option is not supported on Matrox Solios eA/XA Single, eCL/XCL-B, or the standard Camera Link speed (66 MHz) version of Matrox Solios eCL/XCL dual-Base/single-Medium.
Chapter 4: Matrox Solios hardware reference Processing FPGA Depending on your application requirements, you can purchase the board with a Processing FPGA implemented using one of the following two supported FPGA chips.
Processing FPGA 87 Dedicated Processing FPGA memory When you purchase a Matrox Solios with a Processing FPGA, the board also comes with the following memory, which can only be accessed through the Processing FPGA: • 64/128/256 Mbytes of DDR SDRAM at 1.33 Gbytes/sec (2 x 64 bits x 83.3 MHz). • 4/8 Mbytes of QDRII SRAM at 666 Mbytes/sec input, and 666 Mbytes/sec output (2 x 32 bits x 83.3 MHz, in each direction).
Chapter 4: Matrox Solios hardware reference Video to PCI-X bridge The video to PCI-X bridge is capable of high-speed transfers to acquisition memory, to the optional Processing FPGA, and through the PCI-X to PCI-X/PCIe bridge, to Host memory, off-board display memory, or other devices across the Host bus. Upon transmitting the video data, the video to PCI-X bridge can also format the data as follows: • Image resizing. Captured image data can be cropped (ROI capture) or subsampled.
Memory 89 Memory As a standard feature, all Matrox Solios boards except Matrox Solios eCL/XCL-B and Matrox Solios eCL/XCL-F support up to 256 Mbytes of linearly addressable, DDR SDRAM used as acquisition memory. This memory has a bandwidth of up to 1.6 Gbytes/sec when the optional Processing FPGA is installed, and up to 1.32 Gbytes/sec without the optional Processing FPGA installed. As a standard feature, Matrox Solios eCL/XCL-B and eCL/XCL-F also support acquisition memory.
Chapter 4: Matrox Solios hardware reference PCIe/PCI/PCI-X interface Matrox Solios uses PCI-X technology to communicate on-board. PCI-X is a high-performance backwards-compatible enhancement to the conventional PCI bus specification. To communicate with the Host, Matrox Solios XCL and XA can transfer data using either the Host’s PCI or PCI-X bus, depending on the slot used by the board. Matrox Solios eCL and eA can transfer data using the Host’s PCIe bus.
Appendix A: Appendix A: Glossary This appendix defines some of the specialized terms used in the Matrox Solios documentation.
Appendix A: Glossary Glossary • Bandwidth A term describing the capacity to transfer data. Greater bandwidth is needed to sustain a higher transfer rate. Greater bandwidth can be achieved, for example, by using a wider bus. • Blanking period The portion of a video signal after the end of a line or frame, and before the beginning of a new line or frame. During this period, the video signal is "blank" so that a scan line can be brought back to the beginning of the new line or frame.
Glossary 93 • Double buffering Alternating the destination of an operation between two buffers. Double buffering allows you to, for example, process one buffer while grabbing into the other buffer. • Dynamic range The range of values present in a buffer. An unsigned 8-bit buffer, for example, has an allowable range of 0 to 255; its dynamic range can be any range within these values. • Exposure time Refers to the period during which the image sensor of a video source is exposed to light.
Appendix A: Glossary • Grab To acquire an image from a video source. • Horizontal blanking period The portion of a video signal after the end of a line and before the beginning of a new line. During this period, the video signal is "blank". See also vertical blanking period. • Horizontal synchronization signal The part of a video signal that indicates the end of a line and the start of a new one. See also vertical synchronization signal.
Glossary 95 • Progressive scanning Describes a transfer of data in which the lines of the source are written sequentially into the destination buffer. See also interlaced scanning. • QDRII SRAM Quad Data Rate II Static Random Access Memory. A type of memory used for processing. QDRII SRAM allows the Processing FPGA to access data faster than with DDR SDRAM. • Real-time processing The processing of an image as quickly as the next image is grabbed. Also known as live processing.
Appendix A: Glossary • Timer output The signal generated by one of the programmable timers of the frame grabber module. The timer output can be used to control external hardware. For example, it can be fed to the video source to control its exposure time or used to fire a strobe light. • UART Universal Asynchronous Receiver/Transmitter. A component that handles asynchronous communication through a serial interface (for example, RS-232 or LVDS).
Appendix B: Appendix B: Technical information This appendix contains information that might be useful when installing your Matrox Solios board.
Appendix B: Technical information Board summary Global information • Operating system: See your software manual for supported versions of Microsoft Windows. • Computer requirements: - For Matrox Solios eCL and eA, a x4 or x8 PCIe slot; Matrox Solios eCL-B and eA Single can also be used in x1 PCIe slot. For Matrox Solios XCL and XA, an available conventional PCI slot or PCI-X slot. - Processor with an Intel 32-bit architecture (IA32) or equivalent. - A relatively up-to-date PCIe/PCI/PCI-X chipset.
Board summary 99 Technical features of Matrox Solios eCL/XCL Features common to all Matrox Solios eCL/XCL boards • PCIe or PCI/PCI-X short board. Matrox Solios XCL has a universal (3.3 V - 5 V) 64-bit board edge connector; Matrox Solios eCL has a x4 PCIe connector, except for Matrox Solios eCL-B, which has a x1 PCIe connector. • Maximum clock frequency of up to 66 MHz or 85 MHz, depending on the configuration. Clock frequency is also dependent on the length of the cable used.
Appendix B: Technical information • Supports an external rotary encoder with quadrature output.* All Matrox Solios eCL/XCL† boards support 5 V tolerant rotary encoders, except for the standard-speed Matrox Solios XCL dual-Base/single-Medium board (66 MHz), which supports 3.3 V tolerant rotary encoders. Features specific to Matrox Solios eCL/XCL-B • Supports a single video source in the Camera Link Base configuration. It can be a power-over Camera Link (PoCL) video source.
Board summary 101 • Two LVDS auxiliary input signals (trigger input, field polarity input, timer-clock input, quadrature input, or user input). See the Matrox Solios hardware reference chapter for supported configurations. • Two opto-isolated auxiliary input signals (trigger input, field polarity input, or user input). See the Matrox Solios hardware reference chapter for supported configurations. • One LVDS serial port.
Appendix B: Technical information • Four LVDS auxiliary output signals (timer output or user output). See the Matrox Solios hardware reference chapter for supported configurations. • Six TTL auxiliary I/O signals (trigger input, field polarity input, user input, user output, or timer output). See the Matrox Solios hardware reference chapter for supported configurations. • Four LVDS auxiliary input signals (trigger input, field polarity input, timer-clock input, quadrature input, or user input).
Board summary 103 • Instead of being mapped through a LUT, 14- and 16-bit data by-pass the LUTs. • For Matrox Solios eCL/XCL dual-Base/single-Medium in single-Medium mode, 64/128/256 Mbytes of 83 MHz DDR SDRAM used as acquisition memory, with 1.32 Gbytes/sec of memory bandwidth is available. Note that when the optional Processing FPGA is installed or when the fast Camera Link board is used, these numbers increase to 100 MHz and 1.6 Gbytes/sec, respectively.
Appendix B: Technical information Technical features of Matrox Solios eA/XA • PCIe or PCI/PCI-X long board. Matrox Solios XA has a universal (3.3 V - 5 V) 64-bit PCI/PCI-X board edge connector. Matrox Solios eA Quad and Dual have a x4 PCIe connector, while Matrox Solios eA Single has a x1 PCIe connector. • Three factory configured versions: - Single acquisition path (Single). - Two independent acquisition paths (Dual). - Four independent acquisition paths (Quad).
Board summary 105 • One to four independent acquisition paths, depending on the board. Each acquisition path has the following: - Input from one of two software selectable sources. The sources are AC coupled. - Two low-pass filters with cut-offs at 33 MHz and a 7.5 MHz, respectively. - Variable gain amplifier and adjustable offset to set the black and white reference levels. - 10-bit A/D with a 65 MHz sampling rate. - An LVDS/TTL pixel clock input/output. - An LVDS/TTL CSYNC input or HSYNC input/output.
Appendix B: Technical information • 64/128/256 Mbytes of 83 MHz DDR SDRAM used as acquisition memory. 1.32 Gbytes/sec of memory bandwidth. Note that when the optional Processing FPGA is installed, these numbers increase to 100 MHz and 1.6 Gbytes/sec respectively. • Eight TTL/LVDS auxiliary input signals (trigger input, field polarity input, data valid input, timer-clock input, synchronization input, or user input). See the Matrox Solios hardware reference chapter for supported configurations.
Electrical specifications 107 Electrical specifications Matrox Solios eCL/XCL-B (starting from version 000) Operating voltage and current (eCL-B) Typical: 3.3 V, 1 A: 3.3 W Max. PoCL 12.0 V, 0.333 A: 4.0 W* (Current directly drawn from the slot. Power is not dissipated by the board; it is only used by the camera). Total dissipated by the board: 3.3 W Total dissipated by the board and PoCL video sources = 3.3 W + 4.0 W = 7.3 W Operating voltage and current (XCL-B) Typical: 3.3 V, 0 A: 0 W Typical: 5.
Appendix B: Technical information Matrox Solios eCL/XCL-B (starting from version 000) Output signals in TTL format 27 Ohm series termination. High-level output current: -32 mA (max). Low-level output current: +64 mA (max). Output voltage: low of 0.55 V (max); high of 3.0 V (min) at -3 mA, 2.0 V (min) at -32 mA. Opto-coupled input signals 511 Ohm series termination. Input current: • low: 250 μA (max). • high: 5 mA (min) (6.3 mA recommended) to 15 mA (max) (10 mA recommended).
Electrical specifications 109 Matrox Solios eCL/XCL dual-Base/single-Medium (starting from version 100) Output signals in LVDS format No termination. Output current (loaded 100 Ohm): 20 mA (typ). Output voltage (loaded 100 Ohm): • differential: 250 mV (min) to 450 mV (max). • common-mode: 1.125 V (min) to 1.375 V (max). • low: 1.02 V (typ), 0.9 V (min); high: 1.33 V (typ), 1.6 V (max). Input signals in TTL format No termination. Pulled up to 3.3 V with 4.716 k ohm. Clamped to -0.7 V and to 5.7 V.
Appendix B: Technical information Matrox Solios eCL/XCL-F (starting from version 200) Input signals in LVDS format 100 Ohm differential termination. Input current: -10 μA (min) to +10 μA (max). Input voltage: • common-mode: 0.1 V (min) to 2.3 V (max). • differential threshold: low of -100 mV (min); high of 100 mV (max). The following specification applies to the 5 V tolerant LVDS receiver for the rotary encoder*: 100 Ohm differential termination. Input current: -75 μA (min) to +40 μA (max).
Electrical specifications 111 Matrox Solios eA (starting from version 100)/Matrox Solios XA (starting from version 200) Operating voltage and current (XA)* Operating voltage and current (eA) Analog data signal specification Matrox Solios XA Single Matrox Solios XA Dual Matrox Solios XA Quad Typical: 5.0 V, 1.46 A = 7.3 W Typical: 5.0 V, 1.552 A = 7.76 W Typical: 5.0 V, 1.64 A = 8.21 W Typical: 12 V, 0.081 A = 0.975 W Typical: 12 V, 0.203 A = 2.44 W Typical: 12 V, 0.325 A = 3.
Appendix B: Technical information Matrox Solios eA (starting from version 100)/Matrox Solios XA (starting from version 200) Output signals in LVDS format On the analog video input (DVI) connectors: • No termination. • Output current (loaded 100 Ohm): 3.1 mA (typ). • Output voltage (loaded 100 Ohm): - differential: 250 mV (min) to 450 mV (max). - common-mode: 1.125 V (min) to 1.375 V (max). - low of 1.02 V (typ), 0.9 V (min); high of 1.33 V (typ), 1.6 V (max).
Electrical specifications 113 Matrox Solios eA (starting from version 100)/Matrox Solios XA (starting from version 200) Output signals in TTL format On the analog video input (DVI) connectors, for all TTL output signals, except for TTL auxiliary signals that can be configured for timer output: • 22 Ohm series impedance. • High-level output current: -24 mA (max). • Low-level output current: +24 mA (max). • Output voltage: low of 0.55 V (max); high of 2.0 V (min).
Appendix B: Technical information Dimensions and environmental specifications • Dimensions: Board Dimensions Matrox Solios eCL/XCL eCL-B 16.76 L x 6.89 H x 0.16 W cm (6.6" x 2.714" x 0.062") from bottom edge of goldfinger to top edge of board. XCL-B 16.76 L x 6.44 H x 0.16 W cm (6.6" x 2.536" x 0.062") from bottom edge of goldfinger to top edge of board. eCL/XCL dual-Base/single-Medium and eCL/XCL-F 19.05 L x 10.67 H x 0.16 W cm (7.5" x 4.2" x 0.
Connectors on Matrox Solios eCL/XCL-B 115 Connectors on Matrox Solios eCL/XCL-B On the Matrox Solios eCL/XCL-B board, there are several interface connectors. On its bracket, there is one Camera Link video input connector and one auxiliary connector (DBHD-15 or DB-9). On the top edge of the board, there is an internal auxiliary I/O connector.
Appendix B: Technical information Camera Link video input connector The Camera Link video input connector is a 26-pin high-density mini D ribbon (MDR) connector. It is used to receive video input, timing, and synchronization signals and transmit/receive communication signals between the video source and the frame grabber. The pinout of this connector follows the Camera Link standard.
Connectors on Matrox Solios eCL/XCL-B Pin Hardware signal name MIL constant for auxiliary 117 Description signal* 17+,4- CC2 M_CC_IO2 Camera control output 2 for acquisition path 0, which suppor ts: timer output (M_TIMER1/M_TIMER2 on M_DEV0), user output (M_USER_BIT_CC_IO0/M_USER_BIT_CC_IO1 on M_DEV0), VSYNC, HSYNC, clock output, or rerouting of specific auxiliary input signals†. 20+,7- SerTC Serial port to video source (UART). 26 Inner shield Ground, or for PoCL cables, +12 V. *.
Appendix B: Technical information The pinout for the auxiliary I/O connector is as follows.
Connectors on Matrox Solios eCL/XCL-B Pinout for DBHD-15 Pinout for DB-9 Hardware signal name 13+,14- - P0_LVDS_AUX_OUT0 15+,9- 7+,2- - 9 MIL constant for 119 Digitizer device number for auxiliary signal Description M_AUX_IO12 M_DEV0 LVDS auxiliary signal (output) for acquisition path 0, which supports: timer output (M_TIMER1 on M_DEV0) or user output (M_USER_BIT0).
Appendix B: Technical information Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards On the Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards, there are several interface connectors. On its bracket, there are two Camera Link video input connectors. On the top edge of the board, there is an internal auxiliary I/O connector and, if the board has the optional Processing FPGA, a JTAG connector.
Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards 121 Camera Link video input connectors The two Camera Link video input connectors are 26-pin high-density mini D ribbon (MDR) connectors. They are used to receive video input, timing, and synchronization signals and transmit/receive communication signals between the video source and the frame grabber. The pinout of these connectors follow the Camera Link standard.
Appendix B: Technical information Pin Hardware signal name MIL constant for auxiliary Description signal* 12+,25- X0 Video input data X0. 13 Inner shield Ground. 14 Inner shield Ground. 15+,2- CC4 M_CC_IO4 Camera control output 4 for acquisition path 0, which supports: timer output (M_TIMER1/M_TIMER2 on M_DEV0), user output (M_USER_BIT_CC_IO0/M_USER_BIT_CC_IO1 on M_DEV0), VSYNC, HSYNC, clock output, or rerouting of specific auxiliary input signals† .
Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards 123 When the board is configured in single-Medium or single-Full mode, the first connector has the pinout described above, while the second connector has the following pinout. Pin Hardware signal name Description 1 Inner shield Ground (inner shield), or +12V to camera in PoCL mode. 2+,15- Z3 Video input data Z3.* 3+,16- Zclk+ Clock input Z.* 4+,17- Z2 Video input data Z2.* 5+,18- Z1 Video input data Z1.
Appendix B: Technical information External auxiliary I/O connector 0 External auxiliary I/O connector 0 is a high-density D-subminiature 44-pin (DBHD-44*) female connector, located on the bracket of the cable adapter board. It is used to transmit timing and synchronization signals, and transmit/receive auxiliary signals. It interfaces with the 50-pin internal auxiliary I/O connector on the board, making the I/O signals accessible outside the computer enclosure.
Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards Pin Hardware signal name MIL constant for auxiliary signal* Digitizer device number for auxiliary signal Description 125 12+,28- LVDS_AUX_IN1 M_AUX_IO5 M_DEV0/ M_DEV1 LVDS auxiliary signal (input), shared between both acquisition paths for trigger input (trigger controller 3 on acq path 0; 3 or 1 on acq path 1) or user input, and dedicated to acquisition path 1 for timer clock input or quadrature input bit 1.
Appendix B: Technical information Pin Hardware signal name MIL constant for Digitizer device number for auxiliary signal Description auxiliary signal* 36+,21- P1_LVDS_VSYNC_OUT N/A N/A VSYNC output for acq. path 1. 37+,23- P0_LVDS_AUX_IN1 M_AUX_IO11 M_DEV0 LVDS auxiliary signal (input) for acquisition path 0, which supports: trigger input (trigger controller 1 on acq path 0), user input, timer clock input, or quadrature input bit 1.
Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards 127 External auxiliary I/O connector 1 External auxiliary I/O connector 1 is a standard D-subminiature (DB-9*) female connector, located on the bracket of the cable adapter board. It is used to transmit/receive auxiliary signals. It interfaces with the 50-pin internal auxiliary I/O connector on the board, making the I/O signals accessible outside the computer enclosure. The pinout for this connector is as follows.
Appendix B: Technical information To build your own cable, you can purchase the following parts: Mating information Manufacturer: NorComp, Inc. Connector: 180-015-203L001 Backshell: 970-015-010-011 These parts can be purchased from third parties such as Digi-Key Corporation (www.digikey.com). Internal auxiliary I/O connector The internal auxiliary I/O connector is a 50-pin low-profile IDC connector.
Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards Pin Hardware signal name MIL constant for auxiliary signal * Digitizer device number for auxiliary signal Description 129 A6 P0_TTL_AUX_IO_0 M_AUX_IO8 M_DEV0 TTL auxiliary signal (input/output) for acquisition path 0, which supports: timer output (M_TIMER3 on M_DEV0), trigger input (trigger controller 0 on acq path 0), user input, user output (M_USER_BIT2), or field polarity input.
Appendix B: Technical information Pin Hardware signal name MIL constant for auxiliary signal * A18 TTL_AUX_IO_1 A19, B19 P0_LVDS_CLK_OUT M_AUX_IO3 Digitizer device number for auxiliary signal Description M_DEV0/ M_DEV1 TTL auxiliary signal (input/output), shared between both acquisition paths for trigger input (trigger controller 3 on acq path 0; 3 on acq path 1), user input, or user output (M_USER_BIT5), and dedicated to acquisition path 1 for timer output (M_TIMER2 on M_DEV1).
Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards 131 JTAG connector If Matrox Solios eCL/XCL has the optional Processing FPGA, the board features a 10-pin male JTAG connector for debugging and probing internal signals of the FPGA. The pin assignment, as used in JTAG mode, is as follows: 2 10 1 9 Pin Hardware signal name Description 1 TCK Clock signal. 2 GND Signal ground. 3 TDO Data from device. 4 VCC(TRGT) Target power supply.
Appendix B: Technical information Connectors on Matrox Solios eA/XA On the Matrox Solios eA/XA board, there are several interface connectors. On its bracket, there are two analog video input connectors (DVI type). On the top edge of the board, there is an internal auxiliary I/O connector and an optional JTAG connector.
Connectors on Matrox Solios eA/XA 133 Analog video input connectors The two analog video input connectors are DVI dual-video-input female connectors. They are used to receive video input signals and transmit/receive timing, synchronization, and communication signals between the video source and the frame grabber.
Appendix B: Technical information MIL constant for Digitizer device number for auxiliary signal Pin Hardware signal name * 8 P1_RS232_TxD RS-232 serial output from acq. path 1 (UART) to video source. 10+, 9- P1_LVDS/TTL_CHSYNC_IO CSYNC input or HSYNC input/output for acq. path 1. 11 GND Ground. 13+, 12- P0_LVDS/TTL_CHSYNC_IO CSYNC input or HSYNC input/output for acq. path 0. 14 P0_TTL_AUX(TRIG)_IN 15 GND Ground. 16 P0_RS232_TxD RS-232 serial output from acq.
Connectors on Matrox Solios eA/XA 135 The pinout for DVI connector 1 is as follows: MIL constant for Digitizer device number for auxiliary signal Pin Hardware signal name* 2+, 1- P3_LVDS/TTL_VSYNC_IO VSYNC input/output for acq. path 3. 3 GND Ground. 5+, 4- P2_LVDS/TTL_VSYNC_IO 6 P3_TTL_AUX(EXP)_OUT 7 P3_RS232_RxD RS-232 serial input to acq. path 3 of frame grabber (UART). 8 P3_RS232_TxD RS-232 serial output from acq. path 3 (UART) to video source.
Appendix B: Technical information MIL constant for Digitizer device number for auxiliary signal Pin Hardware signal name* 24 P2_RS232_RxD RS-232 serial input to acq. path 2 of frame grabber (UART). C1 P0_VID_IN_B Video input B for acq. path 0 (AC/DC). C2 P1_VID_IN_B Video input B for acq. path 1 (AC/DC). C3 P2_VID_IN_B Video input B for acq. path 2 (AC/DC). C4 P3_VID_IN_B Video input B for acq. path 3 (AC/DC). C5 GND Ground. C6 GND Ground. M1 GND Ground. M2 GND Ground.
Connectors on Matrox Solios eA/XA 137 In addition, all the signals can be either LVDS or TTL; when TTL, they are expected on the pin denoted as positive. The pinout for this connector is as follows. The description of each auxiliary signal states whether the signal is specific to an acquisition path and the type of signals that can be routed onto it.
Appendix B: Technical information Pin Hardware signal name* MIL constant for Digitizer device number for auxiliary signal Description 8+,24- LVDS/TTL_AUX_IN2 M_AUX_IO4 M_DEV0/ M_DEV1/ M_DEV2/ M_DEV3 LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger input (trigger controller 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3) or user input, and dedicated to acquisition path 1 for field polarity, data valid, CSYNC, or HSYNC input.
Connectors on Matrox Solios eA/XA 139 Pin Hardware signal name* MIL constant for auxiliary signal† Digitizer device number for auxiliary signal Description 36 GND N/A N/A Ground. 37 GND N/A N/A Ground.
Appendix B: Technical information External auxiliary I/O connector 1 External auxiliary I/O connector 1 is a standard D-subminiature 9-pin (DB-9*) female connector, located on the bracket of the LVDS cable adapter board. It is used to receive opto-isolated auxiliary input signals. It interfaces with the 50-pin internal auxiliary I/O connector on the board, making the auxiliary signals accessible outside the computer enclosure. The pinout for this connector is as follows.
Connectors on Matrox Solios eA/XA 141 To build your own cable, you can purchase the following parts: Manufacturer: NorComp, Inc. Connector: 172-E09-102-031 Backshell: 970-009-010-011 These parts can be purchased from third parties such as Digi-Key Corporation (www.digikey.com). Internal auxiliary I/O connector The internal auxiliary I/O connector is a 50-pin low-profile IDC connector.
Appendix B: Technical information Pin A25 Pin B25 Pin A1 Board side Pin B1 Pin Hardware signal name* Description Pin Hardware signal name* Description A1 5V 5 V power. B1 5V 5 V power. A2 GND Ground. B2 P0_LVTTL_CLK_OUT Clock output for acq. path 0. A3 GND Ground. B3 P0_LVTTL_CLK_IN Clock input for acq. path 0. A4 GND Ground. B4 P1_LVTTL_CLK_OUT Clock output for acq. path 1. A5 GND Ground. B5 P1_LVTTL_CLK_IN Clock input for acq. path 1. A6 GND Ground.
Connectors on Matrox Solios eA/XA 143 Pin Hardware signal name* Description Pin Hardware signal name* Description A20 LVTTL_AUX_IN0 Auxiliary input 0 for an unspecified acq. path. B20 LVTTL_AUX_IN1 Auxiliary input 1 for an unspecified acq. path. A21 LVTTL_AUX_IN2 Auxiliary input 2 for an unspecified acq. path. B21 LVTTL_AUX_IN3 Auxiliary input 3 for an unspecified acq. path. A22 LVTTL_AUX_IN4 Auxiliary input 4 for an unspecified acq. path.
Appendix B: Technical information JTAG connector If Matrox Solios eA/XA has the optional Processing FPGA, the board features a 10-pin male JTAG connector for debugging and probing internal signals of the FPGA. The pin assignment, as used in JTAG mode, is as follows: 2 10 1 9 Pin Signal Description 1 TCK Clock signal. 2 GND Signal ground. 3 TDO Data from device. 4 VCC(TRGT) Target power supply. 5 TMS JTAG state machine control. 6 No connect No connect.
Appendix C: Appendix C: Major revisions of Matrox Solios boards This appendix lists the major revisions of the Matrox Solios boards that are RoHS-compliant.
Appendix C: Major revisions of Matrox Solios boards Major revisions of Matrox Solios RoHS-compliant versions of Matrox Solios eA/XA Part number SOL6M1A* SOL6M1AS* SOL6M2A* SOL6M2AE* SOL6M4A* Version Description 200 First shipping version. 201 Moved to secondary source for A/D. This was done to ensure availability. 202 Improved product packaging. 203 Added pull-up resistors to the interface of the CPLD. This was a preventive action. 204 Moved to primary source for A/D.
Major revisions of Matrox Solios 147 RoHS-compliant versions of Matrox Solios eA/XA Part number Version Description SOL6M4AE* 100 First shipping version. 101 Upgraded the PCI-X to PCIe bridge to a new version. This was a corrective action. For more information, refer to product bulletin MIPB-67. 102 Modified the power-up sequence of the PCIe bridge. This was a corrective action. For more information, refer to product bulletin MIPB-77. 103 Moved to secondary source for A/D.
Appendix C: Major revisions of Matrox Solios boards RoHS-compliant versions of Matrox Solios eCL/XCL Part number Version Description SOL6MCL* 100 First shipping version. 101 Set a default clock speed to improve testability. 102 Changed product packaging. 103 Changed a TTL buffer of a TTL auxiliary output signal to one with a higher voltage tolerance. This was a preventive action. 100 First shipping version. 101 Upgraded the PCI-X to PCIe bridge to a new version.
Major revisions of Matrox Solios 149 RoHS-compliant versions of Matrox Solios eCL/XCL Part number Version Description SOL6MFCE* 100 First shipping version. 101 Replaced the LVDS receiver to suppor t 5 V LVDS auxiliary input signals (required to support most rotary encoders). This was done to enhance the feature set. For more information, refer to product bulletin MIPB-56. 104 Modified the power-up sequence of the PCIe bridge. This was a corrective action.
Appendix C: Major revisions of Matrox Solios boards
Appendix D: Appendix D: Acknowledgments This appendix lists the copyright information regarding third-party material used to implement components on the Matrox Solios board.
Appendix D: Acknowledgments UART copyright information The following is the copyright notice for the UART design used on the Matrox Solios boards. Copyright © 2002 Daniel Wallner (jesus@opencores.org) All rights reserved. Redistribution and use in source and synthesized forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer.
Index A A/D converters, Matrox Solios eA/XA 75 AC coupling, Matrox Solios eA/XA 73 acquisition features Matrox Solios eA/XA 13, 70 Matrox Solios eCL/XCL 8, 46 acquisition path, defined 45 acquisition paths Matrox Solios eA/XA 72 Matrox Solios eCL/XCL 10, 46 adapter board Matrox Solios eA/XA 21, 27, 29–30 Matrox Solios eCL/XCL 21, 27, 29–30 adapter bracket 27, 29–30 analog input 72 analog video input connectors 133 analog-to-digital converters see A/D converters, Matrox Solios eA/XA attenuator, Matrox Solios
H hardware reference 44 horizontal blanking period defined 94 horizontal synchronization defined 94 horizontal synchronization signals 76–77 Host 18 I independent acquisition path 45 installation hardware 26 multiple boards 40 overview 22 interlaced scanning defined 94 internal auxiliary I/O connectors 128, 141 J JTAG connector 131, 144 L LED 17 line-locked mode 77 low-pass filters, Matrox Solios eA/XA 75 LUTs 54 defined 94 Matrox Solios eA/XA 75 Matrox Solios eCL/XCL 55 Matrox Solios eCL/XCL-B 54, 100 M
Matrox Solios eCL/XCL 8, 16, 33, 99, 131 acquisition features 8, 46 acquisition paths 10, 46 acquisition rate 47 auxiliary signals 63 camera control output signals 63 ChannelLink receivers 53 communication 55 connectors 115, 120 demultiplexer 54 dimensions 114 LUTs 55 pixel clock 67 synchronization 67 synchronization and control signals 56 timer output 65 video sources supported 52 video timing information 47 Matrox Solios eCL/XCL dual-Base/single-Medium 10, 108, 120 connectors 120 Matrox Solios eCL/XCL-B 9
T technical features Matrox Solios eA/XA 104 Matrox Solios eCL/XCL 99 Matrox Solios eCL/XCL-B 99 Matrox Solios eCL/XCL-F 99 technical specifications 98 timer output defined 96 Matrox Solios eA/XA 82 Matrox Solios eCL/XCL 65 transfer to/from the Host buffer data 18, 90 triggers Matrox Solios eA/XA 83 U UART 16, 56, 76 defined 96 V vertical blanking period 96 vertical synchronization defined 96 vertical synchronization signals 76 video input connector 133 video sources supported Matrox Solios eCL/XCL 10, 46
Regulatory Compliance FCC Compliance Statement Warning Changes or modifications to these units not expressly approved by the party responsible for the compliance could void the user's authority to operate this equipment. The use of shielded cables for connections of these devices to other peripherals is required to meet the regulatory requirements. Note These devices comply with Part 15 of FCC Rules. Operation is subject to the following two conditions: 1.
This device complies with EC Directive 89/336/EEC for Class A digital devices. They have been tested and found to comply with EN55022/CISPR22 and EN55024/CISPR24 when installed in a typical class A compliant host system. It is assumed that these devices will also achieve compliance in any Class A compliant system. Ces unités sont conformes à la Directive communautaire 89/336/EEC pour les unités numériques de Classe A.
Limited Warranty Refer to the warranty statement that came with your product.
