VXI-MXI User Manual October 1993 Edition Part Number 320222-01 © Copyright 1989, 1993 National Instruments Corporation. All Rights Reserved.
National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, TX 78730-5039 (512) 794-0100 (800) 433-3488 (toll-free U.S.
Limited Warranty The National Instruments MXIbus boards and accessories are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
FCC/DOC Radio Frequency Interference Compliance This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the instructions in this manual, may cause interference to radio and television reception. This equipment has been tested and found to comply with the following two regulatory agencies: Federal Communications Commission This device complies with Part 15 of the Federal Communications Commission (FCC) Rules for a Class A digital device.
Contents About This Manual ............................................................................................................... xi Organization of This Manual ........................................................................................... xi How to Use This Manual ................................................................................................ xii Related Documentation ...................................................................................................
Contents Chapter 4 Register Descriptions .........................................................................................................4-1 Register Maps ................................................................................................................4-1 Register Sizes .....................................................................................................4-1 Register Description Format ..............................................................................
Contents Chapter 6 Theory of Operation ..........................................................................................................6-1 VMEbus Address and Address Modifier Transceivers..................................................6-1 VXIbus System Controller Functions ............................................................................6-1 VMEbus Data Transceivers ...........................................................................................
Contents Figures Figure 1-1. Figure 1-2. VXI-MXI Interface Module .............................................................................1-2 VXI-MXI Interface Module with INTX Option...............................................1-3 Figure 2-1. Figure 2-2. VXI-MXI Block Diagram.................................................................................2-6 VXI-MXI INTX Daughter Card Option Block Diagram .................................
Contents Figure 6-1. Figure 6-2. Master to Slave VMEbus/MXIbus Transfers ...................................................6-7 Deadlock Situation............................................................................................6-10 Figure C-1. Figure C-2. Figure C-3. VXI-MXI Parts Locator Diagram.....................................................................C-2 VXI-MXI INTX Parts Locator Diagram (Rear View) .....................................
About This Manual The VXI-MXI User Manual describes the functional, physical, and electrical aspects of the VXI-MXI and contains information concerning its operation and programming. Organization of This Manual The VXI-MXI User Manual is organized as follows: • Chapter 1, General Information, describes the VXI-MXI features, lists the contents of your VXI-MXI kit, and explains how to unpack the VXI-MXI kit.
About This Manual How to Use This Manual If you will be installing your VXI-MXI into a system with a VXIbus Resource Manager, you only need to read Chapters 1 through 3 of this manual. If you have more than two VXI-MXIs extending your system, you will find useful system configuration information in Chapter 5. Appendix E is a quick reference for users who have a system containing two mainframes linked by VXI-MXI modules.
Chapter 1 General Information This chapter describes the VXI-MXI features, lists the contents of your VXI-MXI kit, and explains how to unpack the VXI-MXI kit. The VXI-MXI interface is a C-size extended class mainframe extender for the VXIbus (VMEbus Extensions for Instrumentation). It extends the VXIbus architecture outside a VXIbus mainframe via the MXIbus (Multisystem Extension Interface bus).
General Information Chapter 1 Figure 1-1.
Chapter 1 General Information Figure 1-2.
General Information Chapter 1 Overview The VXI-MXI is an extended class Register-Based VXIbus device with optional Slot 0 capability so that it can reside in any slot in a C-size or D-size VXIbus chassis. The VXI-MXI converts A32, A24, A16, D32, D16, and D08(EO) VXIbus bus cycles into MXIbus bus cycles and vice versa. The VXI-MXI has four address windows that map into and out of the VXIbus mainframe.
Chapter 1 – – – • Access to A16, A24, and A32 address space D08(EO), D16, and D32 accesses Release-on-Request bus requester (jumper-selectable arbitration level) VMEbus slave accesses: – – • Data transfer bus arbiter (PRI ARBITER) Interrupt acknowledge daisy-chain driver Pushbutton system reset switch VMEbus master capabilities: – – – • General Information A16, A24, and A32 address space D08(EO), D16, and D32 accesses VXIbus Slot 0 functions: – – – 10 MHz clock MODID register TTL and ECL Trigger
General Information Chapter 1 What Your Kit Should Contain Your VXI-MXI kit should contain the following components: Component Part Number Standard VXI-MXI Interface Module or Enhanced VXI-MXI Interface Module with INTX option 181045-01 181045-02 VXI-MXI User Manual 320222-01 Optional Equipment Equipment Part Number Type M1 MXIbus Cables Straight-point connector to straight-point connector: – 1m – 2m – 4m – 8m – 20 m 180758-01 180758-02 180758-04 180758-08 180758-20 Type M2 MXIbus Cables Straig
Chapter 1 General Information The following optional equipment is also available and may be necessary if your VXI-MXI includes the INTX daughter card.
Chapter 2 General Description This chapter contains the physical and electrical specifications for the VXI-MXI and describes the characteristics of key interface board components. Electrical Characteristics All integrated circuit drivers and receivers used on the VXI-MXI meet the requirements of the VMEbus specification.
General Description Chapter 2 Table 2-1. VXI-MXI VMEbus Signals (Continued) Bus Signals Driver Device Part Number Receiver Device Part Number – LS540 GAL20V8 – AS760, LS145 LS540 IACKIN* IACKOUT* IRQ[7-1]* All MXIbus transceivers meet the requirements of the MXIbus specification. Table 2-2 lists the components used. Table 2-2.
Chapter 2 General Description The VXI-MXI does not support the following VMEbus modules: • Serial Clock Driver • Power Monitor Table 2-3 indicates the VXI-MXI VMEbus compliance levels. Table 2-3.
General Description Chapter 2 Table 2-3.
Chapter 2 General Description VXI-MXI Functional Description In simplest terms, the VXI-MXI can be thought of as a bus translator that converts VXIbus signals into appropriate MXIbus signals. From the perspective of the MXIbus, the VXI-MXI implements a MXIbus interface to communicate with other MXIbus devices. From the perspective of the VMEbus, the VXI-MXI is an interface to the outside world. Figure 2-1 is a functional block diagram of the VXI-MXI.
General Description Chapter 2 Daughter Card Connection IRQ7-1 SYSFAIL* SYSRESET* ACFAIL* SYSFAIL, ACFAIL, SYSRESET Logic IRQ* Interrupt Circuitry VMEbus IRQ7-1 A32 Window MXIbus Address/Dat a and Address Modifiers Transceivers A24 Window VXIbus VXIbus System Controller Functions D31-0 VMEbus Data Transceivers A16 Window LA Window AM4-0 MXIbus System Controller Functions VXI-MXI Configuration Registers VMEbus Control Signals Transceivers MXIbus Master Mode State Machine MXIbus Control Sign
Chapter 2 General Description • Interrupt Circuitry This circuitry generates and receives interrupt requests on the VMEbus, the MXIbus, and on boards plugged into the daughter card connectors. Interrupt requests routed between VXIbus mainframes can be transparently serviced by interrupt handlers in VXIbus mainframes other than the requester's own mainframe. • Parity Check and Generation This circuitry checks and generates MXIbus parity.
General Description Chapter 2 The following information applies only to VXI-MXI kits that include the INTX daughter card option. Figure 2-2 is a block diagram of the circuitry of the INTX daughter card. VX I-MXI CONNECTION INTX Registers Trigger Control INTX Interrupt Control System Resets Control CLK10 Control Figure 2-2.
Chapter 2 • Interrupt Control General Description The interrupt control logic maps the VMEbus interrupt lines to and from the corresponding INTX interrupt lines. In conjunction with the VXI-MXI circuitry, the interrupt requests routed between VXIbus mainframes through the INTX connector can be transparently serviced by interrupt handlers in VXIbus mainframes other than the mainframe from which the request was generated. This process takes advantage of transparent MXIbus interrupt acknowledge cycles.
Chapter 3 Configuration and Installation This chapter describes the configuration and installation of the VXI-MXI. Configuring the VXI-MXI Before installing the VXI-MXI in the VXIbus mainframe, configure the VXI-MXI to suit the needs for your VXIbus system.
Configuration and Installation Chapter 3 Figure 3-1 shows the locations and factory default settings of the VXI-MXI configuration jumpers and switches for a VXI-MXI without the INTX option. Figure 3-1.
Chapter 3 Configuration and Installation Figure 3-2 shows the locations and factory default settings of the VXI-MXI configuration jumpers and switches for a VXI-MXI with the INTX option. Figure 3-2.
Configuration and Installation Chapter 3 The Metal Enclosure The VXI-MXI is housed in a metal enclosure to improve EMC performance and to provide easy handling. Because the enclosure includes cut-outs to facilitate changes to switch and jumper settings, it should not be necessary to remove it under normal circumstances. Should you find it necessary to open the enclosure, remove the three screws on the top, the three screws on the bottom, and the three screws on the right side panel of the enclosure.
Chapter 3 Configuration and Installation When the VXI-MXI is installed in Slot 0, it becomes the VMEbus System Controller, meaning that it has VMEbus Data Transfer Bus Arbiter capability (PRI ARBITER) and that it drives the 16 MHz VMEbus system clock. The VMEbus Data Transfer Bus Arbiter circuitry accepts bus requests on all four VMEbus request levels, prioritizes the requests, and grants the bus to the highest priority requester.
Configuration and Installation Chapter 3 VXIbus Logical Address Each device in a VXIbus/MXIbus system is assigned a unique number between 0 and 254. This 8-bit number, called the logical address, defines the base address for the configuration registers located on the device. With unique logical addresses, each VXIbus device in the system is assigned 64 bytes of configuration space in the upper 16 KB of A16 space. Some VXIbus devices have dynamically configurable logical addresses.
Chapter 3 Configuration and Installation LOGICAL ADDRESS SWITCH OFF ON 1 2 OFF 1 2 3 4 5 6 7 8 3 4 Shown at Default setting of Logical Address 1 5 6 7 8 Push this side down for logic 0 Push this side down for logic 1 a. Switch Setting to Default Setting Logical Address LOGICAL ADDRESS SWITCH OFF ON 1 2 OFF 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Shown at Default setting of Logical Address 1 Push this side down for logic 0 Push this side down for logic 1 b.
VMEbus Request Level • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • b. Level 2 Requester • • • VMEbus Request Level a. Level 3 Requester (default) • • • VMEbus Request Level • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Chapter 3 • • • Configuration and Installation VMEbus Request Level c. Level 1 Requester d. Level 0 Requester Figure 3-6.
Chapter 3 Configuration and Installation configuration allows VXIbus transfers to have short bus timeout values and MXIbus transfers to have much longer timeout values. You can either disable the VMEbus timeout value or set it to 100, 200, or 400 µs by moving the VME BTO Level jumper, as shown in Figure 3-7. The VMEbus timeout is disabled when a VMEbus cycle maps out of the mainframe, initiating a MXIbus cycle.
Configuration and Installation Chapter 3 VMEbus Timeout Chain Position The VME BTO Chain Position jumper block indicates the location of the VXI-MXI interface in relation to other VXI-MXIs installed in the mainframe. If only one VXI-MXI is in the system, set the jumper block to one of the configurations shown in Figure 3-8. VME BTO Chain Position • • • • • • VME BTO Chain Position • • • • • • • • • • • W7 • • • W7 b. One VXI-MXI, Non-Slot 0 a.
Chapter 3 Configuration and Installation If the system contains more than one VXI-MXI, select which card will supply the VMEbus timeout, and set the jumper block according to the VXI-MXI's position in relation to the adjacent VXI-MXIs. Figure 3-9 shows four possible settings. • • • • • • • • • • • • • • • • c. Non-Slot 0 VXI-MXI with BTO, VXI-MXI Located between Two VXI-MXIs, Multiple VXI-MXIs in Mainframe VME BTO Chain Position • • W7 • • VME BTO Chain Position • • • • • • • b.
Configuration and Installation Chapter 3 For the VXI-MXIs that do not supply the VMEbus timeout, set the VME BTO Chain Position jumper block to reflect each VXI-MXI's position in relation to the adjacent VXI-MXIs. See Figure 3-10. c. Non-Slot 0 VXI-MXI without BTO, VXI-MXI Located between Two VXI-MXIs, Multiple VXI-MXIs in Mainframe (Suggested Configuration) • • • • • • VME BTO Chain Position • • • • • • • • • • • • • • • • • • W7 VME BTO Chain Position • • • • • • • • • b.
Chapter 3 Configuration and Installation Interlocked Arbitration Mode Interlocked arbitration mode is an optional mode of operation in which the system performs as one large VXIbus mainframe with only one master of the entire system (VXIbus and MXIbus) at any given moment. This mode of operation prevents deadlocks by interlocking all arbitration in the VXIbus/MXIbus system. Refer to Chapter 6 for a thorough discussion of interlocked arbitration mode.
Configuration and Installation Chapter 3 Select interlocked arbitration mode by changing the default setting of the slide switch from Normal to Interlocked Bus Cycles as shown in Figure 3-11. Interlocked Bus Cycles Interlocked Bus Cycles S3 S3 Normal Normal a. Normal Operating Mode (Default Setting) b. Interlocked Bus Cycle Mode Figure 3-11.
Chapter 3 Configuration and Installation MXIbus System Controller Enabled S4 Disabled a. Not MXIbus System Controller (Default Setting) MXIbus System Controller Enabled S4 Disabled b. MXIbus System Controller Figure 3-12.
Configuration and Installation Chapter 3 MXIbus System Controller Timeout The MXIbus System Controller is also responsible for the MXIbus system timeout. The timeout period begins when a MXIbus data strobe (DS) is received. The period stops when a MXIbus DTACK or BERR is detected. If a timeout occurs, the MXIbus System Controller sends a MXIbus BERR to clear the MXIbus system.
Chapter 3 Configuration and Installation MXIbus Fairness Option The MXIbus fairness feature ensures that all requesting devices will be granted use of the MXIbus. This feature prevents a high priority MXIbus device from consuming all of the MXIbus bandwidth. If MXIbus fairness is enabled, a MXIbus master will not request the bus until it detects that no other devices are requesting the bus. MXIbus fairness ensures that all MXIbus masters have an equal opportunity to use the MXIbus.
Configuration and Installation Chapter 3 CLK10 Source The VXIbus specification requires that Slot 0 devices supply a clock signal, CLK10, on a differential ECL output. The VXI-MXI can generate the CLK10 signal from an onboard oscillator (10 MHz with a 50% ±5% duty cycle), route an external clock signal from the front panel SMB connector labeled EXT CLK to the CLK10 signal, or receive the CLK10 signal. Use the CLK10 Source Select jumper array to select one of these options, as shown in Figure 3-15.
Chapter 3 Configuration and Installation • • • • • • • • • W9 W10 • Receive CLK10, Non-Slot 0 • • Drive CLK10 from SMB CLK10, Slot 0 • • Drive CLK10 from onboard 10MHz, Slot 0 • CLK10 Source Select a. Onboard 10 MHz VXI-MXI Installed in Slot 0 (Default Setting) • • • • • • • W9 W10 • Receive CLK10, Non-Slot 0 • • Drive CLK10 from SMB CLK10, Slot 0 • Drive CLK10 from onboard 10MHz, Slot 0 • CLK10 Source Select b.
Configuration and Installation Chapter 3 EXT CLK SMB Input/Output If you want to have synchronized CLK10 signals in multiple VXIbus mainframes, you can connect the CLK10 signals of the two mainframes together using the EXT CLK SMB connectors on the front panel of the VXI-MXI. One mainframe should source the CLK10 signal to the SMB connection. The other device receives the CLK10 signal from the SMB connection and drives it on the VXIbus CLK10 lines.
Chapter 3 Configuration and Installation W2 Drive CLK10 from INTX CLK10, Slot 0 (W9 and W10 must be removed) Do Not Drive CLK10 from INTX CLK10 W3 W1 Receive CLK10 from INTX INTX CLK10 Routing Drive CLK10 out INTX a. CLK10 Mapping Disabled (Default Setting) W2 Drive CLK10 from INTX CLK10, Slot 0 (W9 and W10 must be removed) Do Not Drive CLK10 from INTX CLK10 W3 W1 Receive CLK10 from INTX INTX CLK10 Routing Drive CLK10 out INTX b.
Configuration and Installation Chapter 3 The VXI-MXI must be installed in Slot 0 if you want to route the INTX CLK10 signal to the VXIbus CLK10 signal. The CLK10 Source Select jumpers on the VXI-MXI must be set to configure the VXI-MXI to receive the CLK10 because the INTX daughter card will now be sourcing the clock signal. You can configure the VXI-MXI to be installed in any slot when the INTX CLK10 Routing switches are enabled to map the VXIbus CLK10 signal to the INTX connector.
Chapter 3 Configuration and Installation Reset Signal Select The VXI-MXI generates a 200 ms active low pulse both on power-up and when you press the pushbutton system reset switch on the front panel. Using the Reset Signal Select slide switch, you can route the pulse to either VMEbus signal ACFAIL* or SYSRESET*. See Figure 3-19. Reset Signal Select Reset Signal Select S7 S7 ACFAIL* ACFAIL* SYSRESET* SYSRESET* a. SYSRESET* Asserted (Default Setting) b. ACFAIL* Asserted Figure 3-19.
Configuration and Installation Chapter 3 MXIbus Termination VXI-MXI MXIbus Cable VXI Mainframe VXI-MXI PC/AT VXI Mainframe VXI-MXI The MXIbus is a matched impedance bus and requires termination networks at the first and last device in the MXIbus daisy-chain. These terminations minimize reflections caused by impedance discontinuities at the ends of the cables.
Chapter 3 Configuration and Installation networks are not used, you should leave these internal terminators in place. If the VXI-MXI is not going to be an end device, or if you will be using external terminators, remove the terminating resistor networks from their sockets and store them in a safe place in case the MXIbus system changes. Figure 3-21 shows the position of the six MXIbus terminating networks. All six MXIbus networks must be either installed or removed from their sockets.
Configuration and Installation Chapter 3 If the daughter card will be the first or last device in the INTX chain (irrespective of the VXI-MXI's position in the MXIbus chain), you should leave these terminators in place. If the daughter card is not going to be an end device, remove all four terminating resistor networks from their sockets. Store them in a safe place in case your system configuration changes. Figure 3-22 shows an example of a daisy-chained MXIbus and INTX system, including terminators.
Chapter 3 Configuration and Installation • If interlocked mode is used, the VXI-MXIs must be the highest priority VMEbus requesters in their mainframe. However, one, and only one, mainframe in the MXIbus link can have a higher priority VMEbus requester than its VXI-MXIs. • The first and last MXIbus devices in the MXIbus link must be terminated. • No two devices in your VXIbus/MXIbus system can have the same logical address.
Configuration and Installation Chapter 3 Connecting the MXIbus Cable MXIbus devices are daisy-chained together with MXIbus cables. Dual-ended cables are polarized and require proper connection to function properly. The VXI-MXI uses a shielded 62-pin high-density D-subminiature device connector specified in the MXIbus specification. When properly configured, MXIbus cables will dress down and away from the VXIbus mainframe. Ensure that the proper cable ends are connected to the intended devices.
Chapter 3 Configuration and Installation If your MXIbus cable has a single connector on one end and a dual-ended connector on the other end (National Instruments part number 180760-XX or 180761-XX, where XX is the length in meters), you can create a MXIbus system that consists of more than two devices. A MXIbus system is defined as the set of devices physically connected by individual MXIbus cable links.
Configuration and Installation Chapter 3 In a properly configured MXIbus system, the first and last devices in the daisy-chain each have only one cable connected to their device connector. MXIbus devices that are neither the first nor the last device in the daisy-chain have two (and only two) MXIbus cables attached to their device connector.
Chapter 3 Configuration and Installation Keep in mind that a system can contain only one device acting as the VXIbus Resource Manager (RM). It is important that the RM be run only after all other devices in the system have been powered on. Because many RMs execute automatically upon power-up, you must be sure when working with a distributed system to power-on the device containing the RM last.
Chapter 4 Register Descriptions This chapter contains detailed information on the use of the VXI-MXI registers, which are used to configure and control the module's operation. All of these configuration registers are accessible from the VMEbus (in the VXIbus configuration space) and from the MXIbus. If you are not writing your own multiframe Resource Manager routines, you can skip over this chapter. Register Maps The register map for the VXI-MXI configuration registers is shown in Table 4-1 and Figure 4-1.
Register Descriptions Chapter 4 Table 4-1.
Chapter 4 Register Descriptions Offset from Base Logical Address 3E Interrupt Acknowledge 7 3C Interrupt Acknowledge 6 3A 38 Interrupt Acknowledge 5 Interrupt Acknowledge 4 36 Interrupt Ack 3 / Trig Async Ack 34 Interrupt Ack 2 / Trig Sync Ack 32 Interrupt Acknowledge 1 VXI-MXI Defined Registers 30 2E VXI-MXI Reserved MXIbus Trigger Configuration 2C Status / ID 2A 28 Interrupt Status / Control Trigger Mode Register 26 Drive Triggers / Read LA 24 22 MXIbus IRQ Configuration MXIbus Lock Register
Register Descriptions Chapter 4 VXIbus Configuration Registers These registers are defined by the VXIbus specification for all VXIbus devices. VXIbus ID Register VXIbus Address: Base Address + 0 (hex) Attributes: Read Only 15 14 13 0 1 DEVCLASS 12 1 1 ADDR 11 10 9 8 1 1 1 1 7 6 5 4 3 2 1 1 1 MANID 1 1 0 1 1 0 R 0 This register provides information about this device and its configuration. The bits in this register are configured in hardware as shown above.
Chapter 4 11-0r Register Descriptions MANID Manufacturer ID Bits This number uniquely identifies the manufacturer of the VXIbus device. These bits are configured in hardware as hex FF6, the VXIbus manufacturer ID number assigned to National Instruments.
Register Descriptions Chapter 4 Device Type Register VXIbus Address: Base Address + 2 (hex) Attributes: Read Only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1/0 0 0 0 1 MODEL 1 1 1 1 1 1 0 R 0 This register indicates how much VMEbus memory is required by this VXIbus device, and identifies this device with a manufacturer's unique model code. The bits in this register are set in hardware to the values shown above. Hard and soft resets have no effect on this register.
Chapter 4 Register Descriptions VXIbus Status/Control Register VXIbus Address: Base Address + 4 (hex) Attributes: Read/Write 15 1 0 14 MODID* 0 13 12 11 10 0 0 0 0 7 6 5 4 0 0 3 RDY 0 2 PASS 0 EDTYPE VERSION 0 0 9 1 0 1 1 0 8 R ACCDIR 0 W 0 R RESET RESET W This register provides status information about this VXIbus device and provides a bit to force the VXI-MXI into a Soft Reset state. The RESET bit is cleared on a hard reset.
Register Descriptions 7-4r VERSION Chapter 4 VXI-MXI Version Number Bits These bits specify the revision version number of the VXI-MXI according the table below. These bits are read only. Version Number Hex D Hex C Hex B Hex A 3r RDY VXI-MXI Revision Revision D Revision E Revision F Revision G Ready Bit This bit is set to one in hardware to indicate that the device is ready to execute its full functionality. This bit is read only.
Chapter 4 Register Descriptions VXIbus Extender Registers These registers are defined for VXIbus extender devices. MODID Register VXIbus Address: Base Address + 8 (hex) Attributes: Read/Write 15 14 13 12 11 10 9 8 0 0 OUTEN MODID12 MODID11 MODID10 MODID9 MODID8 7 6 5 4 3 2 1 0 MODID7 MODID6 MODID5 MODID4 MODID3 MODID2 MODID1 MODID0 R/W R/W This register provides control and status of the MODID lines when the VXI-MXI is installed in Slot 0.
Register Descriptions Chapter 4 Logical Address Window Register VXIbus Address: Base Address + A (hex) Attributes: Read/Write This register defines the range of logical addresses that are mapped into and out of the VXI-MXI through the MXIbus. This register defines a configuration window in the upper 16 KB of A16 space. These bits are cleared on a hard reset. The CMODE bit in the MXIbus Control Register selects the format of this register.
Chapter 4 Register Descriptions 12-11r/w 1 LAEN LADIR Window Applies to 0 X Disabled 1 0 VXI cycles to MXI cycles 1 MXI cycles to VXI cycles Reserved Bits These bits are reserved and read back as ones. Write a zero when writing to these bits. 10-8r/w LASIZE[2-0] Logical Address Window Size Bits This 3-bit number specifies the number of significant address bits in the LABASE field that are compared when determining if an address is in the logical address window.
Register Descriptions Chapter 4 The Logical Address Window Register has the following format when the CMODE bit is set: 15 14 13 12 11 10 9 LAHIGH7 LAHIGH6 LAHIGH5 LAHIGH4 7 6 5 4 3 2 1 0 LALOW7 LALOW6 LALOW5 LALOW4 LALOW3 LALOW2 LALOW1 LALOW0 LAHIGH3 LAHIGH2 LAHIGH1 Bit Mnemonic Description 15-8r/w LAHIGH[7-0] Logical Address Window Upper Bound Bits 8 LAHIGH0 R/W R/W These bits define the upper limit of the range of MXIbus logical addresses that map into the VXIbus.
Chapter 4 Register Descriptions To accommodate 8-bit devices that write to this register, the window is not enabled until the lower byte of the register is written. Therefore, 8-bit devices should write the upper byte first, then the lower byte.
Register Descriptions Chapter 4 A16 Window Map Register VXIbus Address: Base Address + C (hex) Attributes: Read/Write This register defines the range of addresses in the lower 48 KB of A16 space that is mapped into and out of the VXI-MXI through the MXIbus. Earlier versions of the VXI-MXI required the A16 window to be statically configured with a DIP switch. Now the A16 window can only be dynamically configured with this register. These bits are cleared on a hard reset.
Chapter 4 Register Descriptions 12-11r/w 1 A16EN A16DIR Window Applies to 0 X Disabled 1 0 VXI cycles to MXI cycles 1 MXI cycles to VXI cycles Reserved Bits These bits are reserved and read back as ones. Write a zero when writing to these bits. 10-8r/w A16SIZE[2-0] A16 Window Size Bits This 3-bit number specifies the number of significant address bits in the A16BASE field that are compared when determining if an address is in the A16 window.
Register Descriptions Chapter 4 The A16 Window Map Register has the following format when the CMODE bit is set: 15 14 13 12 11 10 9 8 A16HIGH7 A16HIGH6 A16HIGH5 A16HIGH4 A16HIGH3 A16HIGH2 A16HIGH1 A16HIGH0 R/W 7 6 A16LOW7 A16LOW6 5 4 3 1 2 A16LOW5 A16LOW4 A16LOW3 A16LOW2 A16LOW1 Bit Mnemonic Description 15-8r/w A16HIGH[7-0] A16 Window Upper Bound Bits 0 A16LOW0 R/W These bits define the upper limit of the range of MXIbus A16 addresses that map into the VXIbus.
Chapter 4 Register Descriptions To accommodate 8-bit devices that write to this register, the window is not enabled until the lower byte of the register is written. Therefore, 8-bit devices should write the upper byte first, then the lower byte.
Register Descriptions Chapter 4 A24 Window Map Register VXIbus Address: Base Address + E (hex) Attributes: Read/Write This register defines the range of addresses in A24 space that are mapped into and out of the VXI-MXI through the MXIbus. These bits are cleared on a hard reset. The CMODE bit in the MXIbus Control Register selects the format of this register. If the CMODE bit is 0 (default), a Base/Size window comparison is used to determine the range of addresses in the window.
Chapter 4 Register Descriptions 12-11r/w 1 A24EN A24DIR Window Applies to 0 X Disabled 1 0 VXI cycles to MXI cycles 1 MXI cycles to VXI cycles Reserved Bits These bits are reserved and read back as ones. Write a zero when writing to these bits. 10-8r/w A24SIZE[2-0] A24 Window Size Bits This 3-bit number specifies the number of significant address bits in the A24BASE field that are compared when determining if an address is in the A24 window.
Register Descriptions Chapter 4 The A24 Window Map Register has the following format when the CMODE bit is set: 15 14 13 12 11 10 9 8 A24HIGH7 A24HIGH6 A24HIGH5 A24HIGH4 A24HIGH3 A24HIGH2 A24HIGH1 A24HIGH0 R/W 7 6 A24LOW7 A24LOW6 5 4 3 1 2 A24LOW5 A24LOW4 A24LOW3 A24LOW2 A24LOW1 Bit Mnemonic Description 15-8r/w A24HIGH[7-0] A24 Window Upper Bound 0 A24LOW0 R/W These bits define the upper limit of the range of MXIbus A24 addresses that map into the VXIbus.
Chapter 4 Register Descriptions To accommodate 8-bit devices that write to this register, the window is not enabled until the lower byte of the register is written. Therefore, 8-bit devices should write the upper byte first, then the lower byte.
Register Descriptions Chapter 4 A32 Window Map Register VXIbus Address: Base Address + 10 (hex) Attributes: Read/Write This register defines the range of addresses in A32 space that are mapped into and out of the VXI-MXI through the MXIbus. These bits are cleared on a hard reset. The CMODE bit in the MXIbus Control Register selects the format of this register. If the CMODE bit is 0 (default), a Base/Size window comparison is used to determine the range of addresses in the window.
Chapter 4 Register Descriptions 12-11r/w 1 A32EN A32DIR Window Applies to 0 X Disabled 1 0 VXI cycles to MXI cycles 1 MXI cycles to VXI cycles Reserved Bits These bits are reserved and read back as ones. Write a zero when writing to these bits. 10-8r/w A32SIZE[2-0] A32 Window Size Bits This 3-bit number specifies the number of significant address bits in the A32BASE field that are compared when determining if an address is in the A32 window.
Register Descriptions Chapter 4 The A32 Window Map Register has the following format when the CMODE bit is set: 15 14 13 12 11 10 9 8 A32HIGH7 A32HIGH6 A32HIGH5 A32HIGH4 A32HIGH3 A32HIGH2 A32HIGH1 A32HIGH0 R/W 7 6 A32LOW7 A32LOW6 5 4 3 1 2 A32LOW5 A32LOW4 A32LOW3 A32LOW2 A32LOW1 Bit Mnemonic Description 15-8r/w A32HIGH[7-0] A32 Window Upper Bound 0 A32LOW0 R/W These bits define the upper limit of the range of MXIbus A32 addresses that map into the VXIbus.
Chapter 4 Register Descriptions To accommodate 8-bit devices that write to this register, the window is not enabled until the lower byte of the register is written. Therefore, 8-bit devices should write the upper byte first, then the lower byte.
Register Descriptions Chapter 4 INTX Interrupt Configuration Register (on VXI-MXIs with INTX only) VXIbus Address: Base Address + 12 (hex) Attributes: Read/Write 15 14 13 12 11 0 EINT7EN EINT6EN EINT5EN EINT4EN 7 6 5 4 3 0 EINT7DIR EINT6DIR 10 9 8 EINT3EN EINT2EN EINT1EN 1 2 R/W 0 EINT5DIR EINT4DIR EINT3DIR EINT2DIR EINT1DIR R/W This register on the INTX daughter card is used to configure the mapping of the seven VMEbus interrupts lines to and from the seven INTX interrupt
Chapter 4 Register Descriptions INTX Trigger Configuration Register (on VXI-MXIs with INTX only) VXIbus Address: Base Address + 14 (hex) Attributes: Read/Write 15 ETRG7EN 7 14 13 12 ETRG6EN ETRG5EN ETRG4EN 6 5 4 11 10 9 ETRG3EN ETRG2EN 3 8 ETRG1EN ETRG0EN R/W 1 2 0 ETRG7DIR ETRG6DIR ETRG5DIR ETRG4DIR ETRG3DIR ETRG2DIR ETRG1DIR ETRG0DIR R/W This register on the INTX daughter card is used to configure the mapping of the eight VXIbus TTL trigger lines to and from the eight INTX trigger li
Register Descriptions Chapter 4 INTX Utility Configuration Register (on VXI-MXIs with INTX only) VXIbus Address: Base Address + 18 (hex) Attributes: Read/Write 15 14 13 12 11 10 9 8 0 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 7 6 1 1 5 4 3 2 1 0 R W ACFAILIN ACFAILOUT SYSFAILIN SYSFAILOUT SYSRSTIN SYSRSTOUT R/W This register on the INTX daughter card is used to configure the mapping of the three VMEbus reset signals to and from the three corresponding INTX reset signals.
Chapter 4 5r/w Register Descriptions ACFAILIN Extended ACFAIL Inward Bit Setting this bit enables the INTX ACFAIL line to be mapped into the VMEbus ACFAIL line. Clearing this bit disables the mapping of the INTX ACFAIL line onto the VMEbus ACFAIL line. This bit is cleared on power-up. 4r/w ACFAILOUT Extended ACFAIL Outward Bit Setting this bit enables the VMEbus ACFAIL line to be mapped out onto the INTX ACFAIL line. Clearing this bit disables the mapping of the ACFAIL line onto the INTX ACFAIL line.
Register Descriptions Chapter 4 Subclass Register VXIbus Address: Base Address + 1E (hex) Attributes: Read only 15 14 13 12 11 10 9 1 1 1 1 1 1 1 8 7 1 1 SUBCLASS 6 5 4 3 2 1 1 1 1 1 1 0 0 R 0 These bits define the subclass of a VXIbus extended device. The VXI-MXI is a VXIbus Mainframe Extender. Such devices are assigned the subclass code hex FFFC. Hard and soft resets have no effect on this register.
Chapter 4 Register Descriptions MXIbus Defined Registers MXIbus Status/Control Register VXIbus Address: Base Address + 20 (hex) Attributes: Read/Write 15 14 RMWMODE CMODE 13 1 12 1 11 10 9 8 MXSCTO INTLCK DSYSFAIL FAIR RMWMODE CMODE ECL1EN ECL1DIR ECL0EN ECL0DIR DSYSFAIL DSYSRST 7 6 5 4 3 2 1 0 MXISC MXTRIGINT MXSRSTINT MXACFAILINT LNGMXSCTO MXBERR MXSYSFINT PARERR 0 MXTRIGEN MXSRSTEN MXACFAILEN LNGMXSCTO BOFFCLR 0 0 R W R W This register contains status an
Register Descriptions Chapter 4 MXI Address RMWMODE Modifiers Bit 14r/w CMODE Routing Block X MXIbus block to VMEbus block Non-Block 0 MXIbus RMW cycle to VMEbus RMW cycle 1 MXIbus block to VMEbus single cycle Comparison Mode Bit This bit selects the range comparison mode for the logical address, A16, A24, and A32 Window Mapping Registers. If CMODE is cleared, a Base/Size range comparison is used to determine the range of addresses in the windows.
Chapter 4 11r Register Descriptions MXSCTO MXIbus System Controller Timeout Status Bit If this VXI-MXI is the MXIbus System Controller, this bit is set if the VXI-MXI sent a MXIbus BERR on the last MXIbus transfer in response to a MXIbus System Controller Timeout. This bit is cleared when this register is read and on hard and soft resets.
Register Descriptions 8r FAIR Chapter 4 VXI-MXI Fairness Status Bit When this bit is set, the VXI-MXI is configured as a fair MXIbus requester. If this bit is cleared, the VXI-MXI is configured as an unfair MXIbus requester. FAIR is selected with slide switch S2. This bit is not affected by hard or soft resets. 8w DSYSRST Drive SYSRESET line Bit Setting this bit will cause the VXIbus SYSRESET line to pulse asserted for a minimum of 200 ms.
Chapter 4 4r Register Descriptions MXACFAILINT MXIbus ACFAIL Status Bit When this bit is set, the VXIbus ACFAIL line is active and is being driven across the MXIbus IRQ line. When this bit is cleared, the ACFAIL signal is not driving the MXIbus IRQ line. This bit is cleared on a hard reset. 4w MXACFAILEN MXIbus ACFAIL Enable Bit Setting this bit enables the VXIbus ACFAIL line to be driven across the MXIbus IRQ line. When this bit is cleared, the VXIbus ACFAIL line is not mapped to the MXIbus IRQ line.
Register Descriptions Chapter 4 MXIbus Lock Register VXIbus Address: Base Address + 22 (hex) Attributes: Read/Write 15 1 0 14 1 0 13 1 0 12 1 0 11 10 9 8 1 1 1 1 0 0 0 0 7 6 5 4 3 2 1 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 LOCKED LOCKED R W R W The bit in this register performs differently depending on whether it was accessed by the VMEbus or the MXIbus. This register is cleared on hard and soft resets.
Chapter 4 Register Descriptions MXIbus IRQ Configuration Register VXIbus Address: Base Address + 24 (hex) Attributes: Read/Write 15 14 13 SYSFOUT MIRQ7EN MIRQ6EN 7 SYSFIN 6 5 12 11 10 9 8 MIRQ5EN MIRQ4EN MIRQ3EN MIRQ2EN MIRQ1EN 4 3 2 1 R/W 0 MIRQ7DIR MIRQ6DIR MIRQ5DIR MIRQ4DIR MIRQ3DIR MIRQ2DIR MIRQ1DIR R/W This register either maps the MXIbus IRQ line onto a VMEbus IRQ line, or maps a VMEbus IRQ line onto the MXIbus IRQ line. These bits are cleared on a hard reset.
Register Descriptions VXI-MXI User Manual Chapter 4 MIRQxEN MIRQxDIR 0 X Disabled 1 0 VME IRQ X drives MXI IRQ 1 MXI IRQ drives VME IRQ X 4-38 Routing © National Instruments Corporation
Chapter 4 Register Descriptions Drive Triggers/Read LA Register VXIbus Address: Base Address + 26 (hex) Attributes: Read/Write 15 14 13 12 11 10 DTRIG7 DTRIG6 DTRIG5 DTRIG4 DTRIG3 DTRIG2 7 LADD7 0 6 LADD6 0 5 LADD5 0 4 LADD4 0 3 LADD3 0 2 LADD2 PULSE 9 DTRIG1 1 LADD1 DRVECL1 8 DTRIG0 R/W 0 R LADD0 DRVECL0 W This register provides the logical address of the VXI-MXI and the status of the eight TTL Trigger lines on the VXIbus.
Register Descriptions 1w DRVECL1 Chapter 4 Drive ECL Trigger Line 1 Bit Setting this bit asserts the VXIbus ECL Trigger Line 1 after synchronizing the signal with the 10 MHz clock. 0w DRVECL0 Drive ECL Trigger Line 0 Setting this bit asserts the VXIbus ECL Trigger Line 0 after synchronizing the signal with the 10 MHz clock.
Chapter 4 Register Descriptions Trigger Mode Selection Register VXIbus Address: Base Address + 28 (hex) Attributes: Read/Write 15 1 OMS2 14 1 OMS1 6 7 ECLSTAT0 ECLSTAT1 OTS3 OTS2 13 1 OMS0 12 1 ITS3 5 4 1 1 OTS1 11 1 ITS2 10 1 ITS1 1 ITS0 3 2 TRIGOUT 0 1 ASINT* ASIE TRIGIN ETRIG OTS0 9 8 R 1 ETOEN W 0 R SSINT* SSIE W This register configures the ECL and TTL Trigger lines for interrupt generation and trigger protocol generation. These bits are cleared on soft and hard resets.
Register Descriptions Chapter 4 When in Sync, Semi-Sync, or Async Source Mode, write a zero to the PULSE bit in the Drive Triggers Register to generate a pulse on the trigger line selected by the OTS[3-0] bits. You must write a one to the PULSE bit before another pulse can be generated. In Start-Stop Source Mode, write a zero to the PULSE bit in the Drive Triggers Register to generate a Start signal on the trigger line selected by the OTS[3-0] bits. Writing a one to the PULSE bit generates a Stop signal.
Chapter 4 8w Register Descriptions ETOEN External Trigger Output Enable Bit Setting this bit enables the OMS[2-0] modes to drive the selected trigger line to the TRIG OUT SMB connection. 7r ECLSTAT1 ECL Trigger Line 1 Status Bit Reading this bit returns the current status of ECL Trigger Line 1. 7-4w OTS[3-0] Output Trigger Select Bits These bits select which VXIbus TTL or ECL trigger line is used to route the trigger signal specified by the OMS[2-0] bits.
Register Descriptions 3w ETRIG Chapter 4 Enable Trigger Lines Bit When this bit is set, the protocols selected by the OMS[2-0] bits are enabled to drive the trigger line specified by the OTS[3-0] bits. 2r TRIGOUT Trigger Output Status Bit If this bit is set, the trigger signal routed to the Trigger Out SMB connector on the front panel is high. If this bit is cleared, that trigger signal is low.
Chapter 4 Register Descriptions Interrupt Status/Control Register VXIbus Address: Base Address + 2A (hex) Attributes: Read/Write 15 LINT3 LINT3 14 LINT2 LINT2 7 SYSFAILINT 0 6 IRQ7 DIRQ7 13 LINT1 LINT1 12 ACFAILINT 0 5 4 IRQ6 DIRQ6 IRQ5 DIRQ5 11 10 9 8 R TRIGINT BKOFF SYSFAIL ACFAIL BKOFFIE TRIGINTIE SYSFAILIE ACFAILIE W 3 2 1 0 R IRQ4 IRQ3 IRQ2 IRQ1 DIRQ3 DIRQ4 DIRQ2 DIRQ1 W This register is used to configure local interrupts, drive the VMEbus IRQ lines individually, and reflect the status
Register Descriptions 12r ACFAILINT Chapter 4 VXIbus ACFAIL Interrupt Status Bit If this bit is set, an interrupt is currently driven on the VMEbus interrupt line selected by the LINT[3-1] bits because the VXIbus ACFAIL line became set. This bit is cleared on an interrupt acknowledge cycle for the interrupt level selected by the LINT [3-1] bits. 12w, 7w 0 Reserved Bits These bits are reserved. Write a zero when writing to these bits.
Chapter 4 8r Register Descriptions ACFAIL VXIbus ACFAIL Status Bit This bit reflects the status of the VXIbus ACFAIL line. 8w ACFAILIE VXIbus ACFAIL Interrupt Enable Bit If this bit is set, an interrupt is generated on the VMEbus interrupt line selected by the LINT[3-1] bits when the VXIbus ACFAIL line is set.
Register Descriptions Chapter 4 Status/ID Register VXIbus Address: Base Address + 2C (hex) Attributes: Read/Write 15 14 13 12 11 10 9 8 S15 S14 S13 S12 S11 S10 S9 S8 7 6 5 4 3 2 1 0 S7 S6 S5 S4 S3 S2 S1 S0 R/W R/W This register contains the Status/ID value returned to the Interrupt Handler acknowledging an interrupt request driven by one of the DIRQ bits in the Interrupt Control Register.
Chapter 4 Register Descriptions MXIbus Trigger Configuration Register VXIbus Address: Base Address + 2E (hex) Attributes: Read/Write 15 14 13 12 11 10 TRIG7EN TRIG6EN TRIG5EN TRIG4EN TRIG3EN TRIG2EN 7 6 5 4 3 2 9 8 TRIG1EN TRIG0EN 1 R/W 0 TRIG7DIR TRIG6DIR TRIG5DIR TRIG4DIR TRIG3DIR TRIG2DIR TRIG1DIR TRIG0DIR R/W This register maps the VXIbus TTL Trigger lines to and from the Trigger In and Trigger Out SMB connectors on the front panel of the VXI-MXI.
Register Descriptions Chapter 4 Trigger Synchronous Acknowledge Register VXIbus Address: Base Address + 34 (hex) Attributes: Write Only 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X W W Writing any value to this register reinitializes the SSINT* bit in the Trigger Mode Selection Register.
Chapter 4 Register Descriptions IRQ Acknowledge Registers VXIbus Address: Base Address + 32 (hex) for IRQ1* Base Address + 34 (hex) for IRQ2* Base Address + 36 (hex) for IRQ3* Base Address + 38 (hex) for IRQ4* Base Address + 3A (hex) for IRQ5* Base Address + 3C (hex) for IRQ6* Base Address + 3E (hex) for IRQ7* Attributes: Read Only 15 14 13 12 11 10 9 8 I15 I14 I13 I12 I11 I10 I9 I8 7 6 5 4 3 2 1 0 I7 I6 I5 I4 I3 I2 I1 I0 R R These registers generate a VMEbus interrup
Chapter 5 Programming Considerations This chapter explains important considerations for programming and configuring a VXIbus/ MXIbus system using VXI-MXIs. Note: Detailed descriptions of all register bits can be found in Chapter 4, Register Descriptions. System Configuration In a MXIbus system, MXIbus address space is partitioned between MXIbus devices. A MXIbus device is any device having a MXIbus interface. MXIbus devices can be VXIbus mainframes, personal computers (PCs), or stand-alone instruments.
Programming Considerations Chapter 5 VXIbus Mainframe VXI-MXI VXI-MXI VXIbus Mainframe PC with Multiframe Resource Manager VXI-MXI VXI-MXI MXIbus Interface Root MXIbus Device MXIbus Device VXIbus Mainframe Level 1 Level 2 VXI-MXI VXIbus Mainframe VXIbus Mainframe VXI-MXI VXIbus Mainframe VXI-MXI VXI-MXI Multiframe Resource Manager VXI-MXI VXI-MXI Figure 5-1.
Chapter 5 Programming Considerations The recommended way to set up your system is to fill up Level 1 MXIbus links before adding additional levels. System performance decreases as the number of levels in the system increases because each level requires additional signal conversion. Also keep in mind these three basic rules for VXI-MXI installation as you decide where to install your VXI-MXI interfaces: 1. The VMEbus bus timeout unit must be on a VXI-MXI. 2.
Programming Considerations Base7 Chapter 5 Base6 Base5 Base4 Base3 Base2 Base1 Base0 Size = 1 Size = 2 Size = 3 Size = 4 Size = 5 Size = 6 Size = 7 Figure 5-3. Base and Size Combinations F E D C B A 9 8 7 6 5 4 3 2 1 0 FF-F0 EF-E0 DF-D0 CF-C0 BF-B0 Size = 1 AF-A0 9F-90 8F-80 7F-70 Size = 0 6F-60 5F-50 Size = 2 4F-40 3F-30 Size = 3 2F-20 Size = 4 1F-10 0F-00 Size = 5 Size = 6 Size = 7 Size = 8 Figure 5-4.
Chapter 5 Programming Considerations High/Low Configuration Format Each address mapping window on a MXIbus interface has High and Low address parameters associated with it when the CMODE bit in the MXIbus Control Register is set. The High and Low values define the range of MXIbus addresses that map into the VXIbus. The High bits define the upper bound address of the window, and the Low bits indicate the lower bound address of the window.
Programming Considerations 3. Chapter 5 Next, fill in the blanks for the number of logical addresses required by the first-level MXIbus devices. Using a separate worksheet for each MXIbus link on Level 1, fill in the blanks for the number of logical addresses required by the devices on each MXIbus link. Remember, you do not need to round numbers to the next power of two if you are using the High/Low format for the windows.
Chapter 5 8. Programming Considerations Determine the range of addresses that will be occupied by the root device and each firstlevel device and MXIbus link. For Base/Size systems, use the Logical Address Map Diagram shown in Figure 5-6 to visualize the logical address map for the system. Each square in this diagram represents one logical address. The maximum number of logical addresses in a system is 256 and address ranges are assigned in blocks divisible by a power of two.
Multiframe Resource Manager VXI-MXI Chapter 5 VXI-MXI Programming Considerations VXIbus Mainframe #1 MXIbus #1 MXIbus #2 VXIbus Mainframe #3 VXIbus Mainframe #4 VXIbus Mainframe #6 Level 2 VXI-MXI VXI-MXI MXIbus #3 VXI-MXI VXIbus Mainframe #2 VXI-MXI MXIbus Device B VXI-MXI MXIbus Device A VXI-MXI Level 1 VXIbus Mainframe #5 Figure 5-5. Example VXIbus/MXIbus System Table 5-2.
Chapter 5 Programming Considerations F E D C B A FF-F0 EF-E0 DF-D0 CF-C0 BF-B0 AF-A0 9F-90 8F-80 7F-70 6F-60 5F-50 4F-40 3F-30 2F-20 1F-10 0F-00 9 8 7 6 5 4 3 2 1 Device B 0 Device A VXIbus Mainframe #2 VXIbus Mainframe #5 VXIbus Mainframe #4 VXIbus Mainframe #3 VXIbus Mainframe #6 VXIbus Mainframe #1 MXIbus #1 MXIbus #3 Into VXIbus Mainframe #3 MXIbus #2 Figure 5-6.
Programming Considerations Resource Manager Mainframe: Chapter 5 VXIbus Mainframe #1 Total number of logical addresses required by this device: Round total number up to the next power of two: First Level MXIbus Link: 12 16 (24) Range = Size = 0–F 8-4 = 4 * 101 128 (27) Range = Size = 80 – FF 8-7 = 1 * 8 8 (23) Range = Size = 10 – 17 8-3 = 5 MXIbus #1 (Fill in after completing charts on the following pages) Total number of logical addresses required by MXIbus Link: Round total number up to
Chapter 5 MXIbus Link: Device: Programming Considerations MXIbus #1 MXIbus Device A Range = Size = E0 – E3 8-2 = 6 Range = Size = E0 – E3 8-2 = 6 1 1 (20) Range = Size = E4 8-0 = 8 0 1 1 (20) Range = Size = E4 8-0 = 8 23 32 (25) Range = Size = C0 – DF 8-5 = 3 0 23 32 (25) Range = Size = C0 – DF 8-5 = 3 6 8 (23) Range = Size = 80 – 87 8-3 = 5 32 40 64 (26) Range = Size = A0 – BF 8-6 = 2 Number of logical addresses required by device: 3 Round total number up to the next power of two:
Programming Considerations MXIbus #2 MXIbus Link: Device: Chapter 5 VXIbus Mainframe #6 Number of logical addresses required by device: Round total number up to the next power of two: List other MXIbus links to this mainframe: Number of logical addresses required by additional MXIbus links: + Total number of logical addresses required by this device: = Round total number up to the next power of two: * 7 8 (23) Range = Size = 10 – 17 8-3 = 5 0 7 8 (23) Range = Size = 10 – 17 8-3 = 5 Device: Numbe
Chapter 5 Programming Considerations Worksheets for Planning Your VXIbus/MXIbus Logical Address Map Use the worksheets on the following pages for analyzing your own VXIbus/MXIbus system. Follow the procedures used to fill out the worksheets for the sample VXIbus/MXIbus system.
Programming Considerations Chapter 5 Resource Manager Mainframe: Total number of logical addresses required by this device: Round total number up to the next power of two: * Range = Size = * Range = Size = * Range = Size = * Range = Size = * Range = Size = First Level MXIbus Link: (Fill in after completing charts on the following pages) Total number of logical addresses required by MXIbus Link: Round total number up to next power of two: First Level MXIbus Link: (Fill in after completing chart
Chapter 5 Programming Considerations MXIbus Link: Device: Number of logical addresses required by device: Round total number up to the next power of two: List other MXIbus links to this mainframe: Number of logical addresses required by additional MXIbus links: + Total number of logical addresses required by this device: = Round total number up to the next power of two: * Range = Size = Range = Size = Device: Number of logical addresses required by device: Round total number up to the next power of two
Programming Considerations Chapter 5 MXIbus Link: Device: Number of logical addresses required by device: Round total number up to the next power of two: List other MXIbus links to this mainframe: Number of logical addresses required by additional MXIbus links: + Total number of logical addresses required by this device: = Round total number up to the next power of two: * Range = Size = Range = Size = Device: Number of logical addresses required by device: Round total number up to the next power of two
Chapter 5 Programming Considerations MXIbus Link: Device: Number of logical addresses required by device: Round total number up to the next power of two: List other MXIbus links to this mainframe: Number of logical addresses required by additional MXIbus links: + Total number of logical addresses required by this device: = Round total number up to the next power of two: * Range = Size = Range = Size = Device: Number of logical addresses required by device: Round total number up to the next power of two
Programming Considerations Chapter 5 Alternative Worksheets for Planning Your VXIbus/MXIbus Logical Address Map For most VXIbus/MXIbus systems, you may find the following worksheet helpful when setting up a system using the High/Low format for window configuration. The entire system can be described on one worksheet. The dotted lines can be used to add additional MXIbus links to Level 1 of the system, or to connect a Level 2 MXIbus link to one of the devices on Level 1.
Chapter 5 Programming Considerations Device Device LA's Range IN Lower LA's Lower LA's Lower LA's Lower LA's Lower LA's Lower LA's Lower LA's Lower LA's Range OUT Range OUT Range OUT Range OUT Range OUT Range OUT Range OUT Range OUT MXI#1 Device Device LA's Lower LA's Total LA's Range IN Range OUT Device Device LA's Lower LA's Total LA's Range IN Range OUT Device Device LA's Lower LA's Total LA's Range IN Range OUT Device Device LA's Lower LA's Total LA's Range IN Range OUT Device Devi
Chapter 5 Programming Considerations Planning a VXIbus/MXIbus System A16 Address Map The VXIbus specification does not define a method for dynamically determining the amount of A16 space each device requires. The specification defines the upper 16 KB of A16 space for VXIbus device configuration registers. In most cases, the lower 48 KB of A16 space are used for VMEbus devices installed in the VXIbus system. In a VXIbus/MXIbus system, A16 space is defined as that lower 48 KB of the A16 address space.
Programming Considerations Chapter 5 F0 E0 D0 C0 B0 A0 90 80 70 60 50 40 30 20 10 00 BFFF-B000 Size = 5 Size = 6 Size = 4 AFFF-A000 9FFF-9000 8FFF-8000 7FFF-7000 6FFF-6000 5FFF-5000 4FFF-4000 3FFF-3000 2FFF-2000 1FFF-1000 0FFF-0000 Size = 7 Size = 3 Size = 0 Size = 2 Size = 1 Figure 5-12. A16 Space Allocations for all Size Values To plan the A16 address map, you will follow procedures similar to those for planning the logical address space address map.
Chapter 5 Programming Considerations 4. Figure 5-17 is the worksheet for MXIbus #3, which includes VXIbus Mainframes #4 and #5. Mainframe #4 needs 2 KB and Mainframe #5 needs 1 KB of A16 space. We fill in the appropriate spaces on the worksheet. 5. Now we return to Figure 5-16 and fill in the MXIbus #3 information in the space for a second-level MXIbus link connected to VXIbus Mainframe #3. MXIbus #3 needs 2 KB for Mainframe #4 and 1 KB for Mainframe #5.
Programming Considerations Chapter 5 5000 through 5FFF to MXIbus #3. For the VXI-MXI connected to MXIbus #3, we set Base = 5000, Size = 4 because 4 KB = 256 * 2 8-4, and the direction toward MXIbus #3, or Out. Multiframe Resource Manager VXI-MXI VXI-MXI 14. The 4 KB assigned to MXIbus #3 is further divided between VXIbus Mainframes #4 and #5. We assigned the bottom portion, 5000 to 57FF, to VXIbus Mainframe #4, and the next portion, 5800 to 5BFF, to VXIbus Mainframe #5.
Chapter 5 Programming Considerations Table 5-4.
Programming Considerations Resource Manager Mainframe: Chapter 5 VXIbus Mainframe #1 Amount of A16 space required for this mainframe: Round up to next address break: First Level MXIbus Link: * MXIbus #1 Amount of A16 space required for devices connected to this VXI-MXI: Round up to next address break: 4000 2 A16 Window: Base: Size: Direction: First Level MXIbus Link: 16K 16K 8 KB + 512 * 16K Out MXIbus #2 Amount of A16 space required for devices connected to this VXI-MXI: Round up to next addre
Chapter 5 MXIbus Link: Device: Programming Considerations MXIbus #1 MXIbus Device A Amount of A16 space required by this device: A16 space requirement for each second level MXIbus link connected to this device: + #2 = #1 Round up to next address break: = Total amount of A16 space required for this window: * Round up total amount to the next address size break: First Level VXI-MXI: A16 Window: Base: Size: Direction: Second Level VXI-MXI #1: A16 Window: Base: Size: Direction: Second Level VXI-MXI #2: A16
Programming Considerations MXIbus Link: Device: Chapter 5 MXIbus #3 VXIbus Mainframe #4 Amount of A16 space required by this device: A16 space requirement for each second level MXIbus link connected to this device: + #2 = #1 Round up to next address break: = Total amount of A16 space required for this window: * Round up total amount to the next address size break: First Level VXI-MXI: 5000 5 In A16 Window: Base: Size: Direction: Second Level VXI-MXI #1: A16 Window: Base: Size: Direction: Second Level VX
Chapter 5 Programming Considerations Worksheets for Planning Your VXIbus/MXIbus A16 Address Map Use the worksheets on the following pages for planning an A16 address map for your VXIbus/ MXIbus system. Follow the procedures used to fill out the worksheets for the sample VXIbus/ MXIbus system.
Programming Considerations Chapter 5 Resource Manager Mainframe: Amount of A16 space required for this mainframe: Round up to next address break: * First Level MXIbus Link: Amount of A16 space required for devices connected to this VXI-MXI: Round up to next address break: A16 Window: Base: Size: Direction: * First Level MXIbus Link: Amount of A16 space required for devices connected to this VXI-MXI: Round up to next address break: A16 Window: Base: Size: Direction: * First Level MXIbus Link: Amount
Chapter 5 Programming Considerations MXIbus Link: Device: Amount of A16 space required by this device: A16 space requirement for each second level MXIbus link connected to this device: + #2 = #1 Round up to next address break: = Total amount of A16 space required for this window: * Round up total amount to the next address size break: First Level VXI-MXI: A16 Window: Base: Size: Direction: Second Level VXI-MXI #1: A16 Window: Base: Size: Direction: Second Level VXI-MXI #2: A16 Window: Base: Size: Directi
Programming Considerations Chapter 5 MXIbus Link: Device: Amount of A16 space required by this device: A16 space requirement for each second level MXIbus link connected to this device: + #2 = #1 Round up to next address break: = Total amount of A16 space required for this window: * Round up total amount to the next address size break: First Level VXI-MXI: A16 Window: Base: Size: Direction: Second Level VXI-MXI #1: A16 Window: Base: Size: Direction: Second Level VXI-MXI #2: A16 Window: Base: Size: Directi
Chapter 5 Programming Considerations MXIbus Link: Device: Amount of A16 space required by this device: A16 space requirement for each second level MXIbus link connected to this device: + #2 = #1 Round up to next address break: = Total amount of A16 space required for this window: * Round up total amount to the next address size break: First Level VXI-MXI: A16 Window: Base: Size: Direction: Second Level VXI-MXI #1: A16 Window: Base: Size: Direction: Second Level VXI-MXI #2: A16 Window: Base: Size: Directi
Programming Considerations Chapter 5 MXIbus Link: Device: Amount of A16 space required by this device: A16 space requirement for each second level MXIbus link connected to this device: + #2 = #1 Round up to next address break: = Total amount of A16 space required for this window: * Round up total amount to the next address size break: First Level VXI-MXI: A16 Window: Base: Size: Direction: Second Level VXI-MXI #1: A16 Window: Base: Size: Direction: Second Level VXI-MXI #2: A16 Window: Base: Size: Directi
Chapter 5 Programming Considerations Multiframe RM Operation On power-up, all MXIbus devices are isolated from each other because all address mapping windows are disabled.
Programming Considerations Chapter 5 b. Repeats Step 2 recursively. c. Sets the VXI-MXI inward logical address mapping window to cover the range up to (but not including) the VXI-MXI with the next highest logical address that was found in the logical address space. iv. Sets the VXI-MXI outward logical address mapping window to cover the range of the devices connected to that extender.
Chapter 5 Programming Considerations The RM performs the following steps: 1. Scans logical addresses (0 to FF) and identifies all devices in VXIbus Mainframe #1. Finds the VXI-MXIs at logical addresses 2 and 4 and moves DC devices to the lowest unused logical addresses (for example, 1, 3, 5, 6). 2. Enables the logical address window of the VXI-MXI found at logical address 2 for the entire outward mapping range of 0 to FF.
Programming Considerations Chapter 5 9. Enables the logical address window of the VXI-MXI in VXIbus Mainframe #2 for the entire inward mapping range of 0 to FF. Scans all logical addresses, skipping all previously encountered devices and defined ranges. Finds the Slot 0 device and uses it to move all DC devices in VXIbus Mainframe #2 to the lowest unused logical addresses. No more VXI-MXI interfaces are found.
Chapter 5 Programming Considerations System Administration and Initiation System self-test administration, hierarchy configuration, and initiation of normal operation are handled as defined in the VXIbus specification. A general-purpose multiframe RM must wait five seconds before testing the Passed condition of each device, because no prescribed global mechanism is defined for monitoring all of the SYSFAIL signals in the system.
Chapter 6 Theory of Operation A brief description of the VXI-MXI is given in Chapter 2 along with a functional block diagram (see Figure 2-1). The major elements of the VXI-MXI are discussed in more detail in this chapter. For a detailed discussion of the VXIbus, refer to the VXIbus specification and the VMEbus specification. For a description of MXIbus, refer to the MXIbus specification.
Theory of Operation Chapter 6 VMEbus Control Signals Transceivers The VMEbus control signals transceivers control the sending and receiving of the VMEbus control signals such as address strobe (AS*), the data strobes (DS1*, DS0*), longword (LWORD*), write (WRITE*), data transfer acknowledge (DTACK*), and bus error (BERR*).
Chapter 6 Theory of Operation The Synchronous protocol is a single trigger line broadcast that does not require an acknowledge from its acceptors. The source must assert the trigger for a minimum of 30 ns and allow at least 50 ns between assertions. The rising edge or falling edge can be specified to initiate action in the receiver. The Semi-synchronous protocol uses a single trigger line to communicate between a single source and multiple acceptors.
Theory of Operation Chapter 6 The two trigger interrupt conditions are Trigger Synchronous and Trigger Asynchronous. A synchronous trigger interrupt occurs when the input trigger signal changes from low to high. The asynchronous trigger interrupt occurs when the input trigger signal changes from high to low. These interrupts can be used to receive trigger protocols.
Chapter 6 Theory of Operation Multiple MXIbus devices can interrupt on the same interrupt line; therefore, a MXIbus interrupt acknowledge daisy-chain is required. The MXIbus GIN and GOUT signals are normally used for the arbitration bus grant in/bus grant out daisy-chain. However, when a MXIbus device initiates a MXIbus IACK cycle and drives the MXIbus address modifier code hex 12, the MXIbus GIN and GOUT lines are used as the interrupt acknowledge daisy-chain.
Theory of Operation Chapter 6 The VMEbus interrupt lines can be individually driven by writing to the Interrupt Status/Control Register. When one of these interrupt requests is serviced by an interrupt handler, the information in the Status/ID Register is returned during the IACK cycle and the interrupt request is cleared. Parity Check and Generation All MXIbus devices are required to generate even parity. The VXI-MXI always generates and checks parity on all 32 MXIbus address and data lines.
Chapter 6 Theory of Operation complete when the responding device sends DTACK* and the VXI-MXI releases the data strobe and address strobe. The VXI-MXI interface supports 8-bit, 16-bit, and 32-bit reads and writes across the MXIbus. The least significant data bit maps to MXIbus data line AD00 and the byte orientation on the MXIbus is standard 68000 format.
Theory of Operation Chapter 6 Table 6-3.
Chapter 6 Theory of Operation Table 6-4.
Theory of Operation Chapter 6 VMEbus Slave Master VXIbus Mainframe #2 Slave VXI-MXI VXIbus Mainframe #1 VXI-MXI Master Slave Slave MXIbus VMEbus Figure 6-2. Deadlock Situation If the VXI-MXI responds with a VMEbus BERR* to a transfer initiated by a VXIbus device, the transfer was not completed successfully. The following situations are possible reasons for an unsuccessful transfer: • A MXIbus timeout occurred. • A local timeout occurred.
Chapter 6 Theory of Operation Table 6-3. When a transfer involving an address in one of the inward windows is detected, the VXI-MXI begins arbitrating for the VMEbus. When the VXI-MXI wins the VMEbus, the MXIbus transfer is converted into a VMEbus transfer. The data transfer size information is converted from MXIbus signals to VMEbus signals as shown in Table 6-4.
Theory of Operation Chapter 6 MXIbus specifies trapezoidal bus transceivers to reduce noise and crosstalk in the MXIbus transmission system. These transceivers have open collector drivers that generate precise trapezoidal waveforms with typical rise and fall times of 9 ns. The trapezoidal shape, due to the constant rise and fall times, reduces noise coupling to adjacent lines.
Chapter 6 Theory of Operation All MXIbus masters must have bus request logic for requesting the MXIbus, and the MXIbus System Controller must have bus arbiter logic to grant the bus to requesting masters. Four signals are used for arbitration: bus request (BREQ*), bus grant in (BGIN*), bus grant out (BGOUT*), and bus busy (BUSY*). The MXIbus has a serial, release-on-request arbitration with fairness and bus lock options. In a serial arbitration scheme, devices request the bus by asserting the BREQ* line.
Theory of Operation Chapter 6 For example, if the VXI-MXI owns the VMEbus and it receives a VMEbus bus request from another VXIbus device, the VXI-MXI continues holding the VMEbus and arbitrates for the MXIbus. When it wins the MXIbus, the VXI-MXI can then release the VMEbus so that another VMEbus requester can gain ownership of the VMEbus.
Appendix A Specifications Capability Codes VMEbus Capability Code Description MA32, MA24, MA16 Master Mode A32, A24, and A16 addressing SA32, SA24, SA16 Slave Mode A32, A24, and A16 addressing MD32, MD16, MD08(EO) Master Mode D32, D16, and D08 data sizes SD32, SD16, SD08(EO) Slave Mode D32, D16, and D08 data sizes MBLOCK Master Mode block transfers SBLOCK Slave Mode block transfers MRMW Master Mode Read/Modify/Write SRMW Slave Mode Read/Modify/Write PRI Prioritized arbitration ROR Relea
Specifications Appendix A MXIbus Capability Code Description MA32, MA24, MA16 Master Mode A32, A24, and A16 addressing SA32, SA24, SA16 Slave Mode A32, A24, and A16 addressing MD32, MD16, MD08(EO) Master Mode D32, D16, and D08 data sizes SD32, SD16, SD08(EO) Slave Mode D32, D16, and D08 data sizes MBLOCK Master Mode block transfers SBLOCK Slave Mode block transfers SC Optional MXIbus System Controller FAIR Optional MXIbus fair requester TERM Can accept MXIbus termination resistors IH
Appendix A Specifications Safety Not applicable Shock and Vibration Not applicable Physical Board size Fully shielded VXI C-size board (9.187 in. by 13.386 in.; 233.
Appendix B Mnemonics Key This appendix contains an alphabetical listing of mnemonics used in this manual to describe signals and terminology specific to MXIbus, VMEbus, VXIbus, and register bits. Refer also to the Glossary.
Mnemonics Key Mnemonic Appendix B Type Definition VBS B B B B B B B B B B B B B B B B B B VBS B B VBS B B B B MBS MBS MBS B MBS VMS VBS/MBS B B VME Address Line 1 A16 Window Base Address A16 Window Direction A16 Window Enable A16 Window Upper Bound A16 Window Lower Bound A16 Window Size A24 Window Base Address A24 Window Direction A24 Window Enable A24 Window Upper Bound A24 Window Lower Bound A24 Window Size A32 Window Base Address A32 Window Direction A32 Window Enable A32 Window Upper Bound A32 Win
Appendix B Mnemonics Key Mnemonic Type Definition BTO BUSY* VBS/MBS MBS Bus Timeout Bus Busy VXS B VXIbus 10-MHz System Clock Comparison Mode VBS B B B B MBS VBS VBS B B VBS/MBS B VMEbus Data Lines 31 through 0 VXIbus Device Class Drive IRQ Lines Drive ECL Trigger Line 0 Drive ECL Trigger Line 1 MXIbus Data Strobe VMEbus Data Strobe 0 VMEbus Data Strobe 1 Drive SYSFAIL Drive SYSRESET Data Transfer Acknowledge Drive VXIbus Trigger Lines B B B B B B VXI B B B VME B B B B ECL Trigger Line 0 Direct
Mnemonics Key Mnemonic Appendix B Type Definition B VME VME VME B MXI MBS VBS B Interrupt Acknowledge Status/ID VMEbus Interrupt Acknowledge VMEbus Interrupt Acknowledge Daisy-Chain Input VMEbus Interrupt Acknowledge Daisy-Chain Output Interlocked Bus Operation Interrupt and Trigger Extension Connector MXIbus Interrupt Request VMEbus Interrupt Request Lines Input Trigger Select B B B B B B B B B B VBS Logical Address Window Base Address Logical Address Status Logical Address Window Direction Logical
Appendix B Mnemonic Mnemonics Key Type Definition B B B Output Trigger Mode Select Output Trigger Select MODID Output Enable MBS B B VME B MXIbus Parity Line Parity Error Passed VMEbus Prioritized Arbiter Pulse Selected Trigger Line B B B VME Ready Soft Reset Read/Modify/Write Select Mode Release on Interrupt Acknowledge B MBS B B VME B VME B VME B B B B B B VME B B Status/ID MXIbus Size Signal Synchronous Interrupt Enable Synchronous Interrupt Status VMEbus Interrupt Status/Identification Data
Mnemonics Key Mnemonic Appendix B Type Definition MXI B B B B B B VXI B Terminator Power Trigger Direction Trigger Enable Trigger Input Status Trigger Interrupt Trigger Interrupt Enable Trigger Output Status VXIbus TTL Trigger Lines 7 through 0 VXI-MXI Version Number MBS VBS MXIbus Write VMEbus Write T TERMPWR TRIGDIR[7-0] TRIGEN[7-0] TRIGIN TRIGINT TRIGINTIE TRIGOUT TTLTRG[7-0] VERSION W WR WRITE* VXI-MXI User Manual B-6 © National Instruments Corporation
Appendix C VXI-MXI Component Placement This appendix contains instructions on opening the VXI-MXI module, and removing and reinstalling the optional INTX daughter card. This appendix also contains parts locator diagrams of the VXI-MXI and the INTX daughter card. Removing the Metal Enclosure from the VXI-MXI The VXI-MXI is housed in a metal enclosure to improve EMC performance and to provide easy handling.
VXI-MXI Component Placement Appendix C Figure C-1.
Appendix C VXI-MXI Component Placement Removing the INTX Daughter Card from the VXI-MXI Under normal circumstances you will not need to remove the INTX card from the VXI-MXI module. You have easy access to the INTX terminators and CLK10 mapping switches through cut-outs in the VXI-MXI enclosure. Should you find it necessary to remove the INTX card, follow these steps. 1. Remove the three screws on the top of the daughter card. 2.
VXI-MXI Component Placement Appendix C Figure C-3 is a parts locator diagram of the front side of the INTX daughter card, showing the location of the various components. Figure C-3. VXI-MXI INTX Parts Locator Diagram (Front View) Installing the INTX Daughter Card onto the VXI-MXI When you are ready to reinstall the INTX card onto the VXI-MXI, carefully line up the daughter connection pins to the daughter card sockets on the VXI-MXI and firmly press the connectors together.
Appendix D Connector Descriptions This appendix describes the connector pin assignments for the MXIbus connector and the INTX connector. MXIbus Connector The MXIbus signals are assigned to the device connector as shown in Figure D-1 and Table D-1. 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 Figure D-1. MXIbus Connector Table D-1.
Connector Descriptions Appendix D The MXIbus defines 49 active signals, 12 ground lines, and 1 line for terminator power. Table D-2 describes the signals on the MXIbus connector and groups them in five categories. Table D-2.
Appendix D Connector Descriptions INTX Connector The INTX connector is used only on VXI-MXIs with the INTX daughter card option. The INTX signals are assigned to the device connector as shown in Figure D-2 and Table D-3. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 44 43 42 41 40 39 38 37 36 35 34 33 32 31 Figure D-2. INTX Connector Table D-3.
Connector Descriptions Appendix D Table D-4. INTX Signal Groupings Category Description Signal Name Lines Type § 7 O.C. Interrupts INTX Interrupt IRQ7-1* Triggers INTX Trigger TRIG7-0 +,- 16 Diff Utility Lines INTX SYSRESET INTX SYSFAIL INTX ACFAIL SYSRESET* SYSFAIL* ACFAIL* 1 1 1 O.C. O.C. O.C.
Appendix E Configuring a Two-Frame System This appendix describes how to configure a system containing two mainframes linked by VXI-MXI modules. Configuring VXI-MXIs for a Two-Frame System The factory configuration of the VXI-MXI is suitable for the most common system configurations. However, a VXI system using VXI-MXI modules to extend from one mainframe to another requires that you reconfigure the VXI-MXIs.
Configuring a Two-Frame System Appendix E Figure E-2 shows the necessary settings of the VXI-MXI configuration jumpers and switches for a VXI-MXI without the INTX option installed in Frame A. Figure E-2.
Appendix E Configuring a Two-Frame System Figure E-3 shows the necessary settings of the VXI-MXI configuration jumpers and switches for a VXI-MXI without the INTX option installed in Frame B. Figure E-3.
Configuring a Two-Frame System Appendix E Figure E-4 shows the necessary settings of the VXI-MXI configuration jumpers and switches for a VXI-MXI with the INTX option installed in Frame A. Figure E-4.
Appendix E Configuring a Two-Frame System Figure E-5 shows the necessary settings of the VXI-MXI configuration jumpers and switches for a VXI-MXI with the INTX option installed in Frame B. Figure E-5.
Configuring a Two-Frame System Appendix E Configuration Requirements for Two-Frame System This section contains miscellaneous information you need to consider as you configure a two-frame system. BTO Unit Notice that although the VXI-MXI in Frame A is not the VXI System Controller (not a Slot 0 device) it still has the VXI BTO unit. This VXI-MXI is, however, the MXIbus System Controller and therefore has the MXI BTO unit as well.
Appendix F Customer Communication For your convenience, this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation. Filling out a copy of the Technical Support Form before contacting National Instruments helps us help you better and faster. National Instruments provides comprehensive technical assistance around the world. In the U.S.
Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
VXI-MXI Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item. Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
Other Products • Other MXIbus Devices in System Manufacturer • Function Slot Logical Address Model Function Slot Logical Address Other VXIbus Devices Manufacturer • Model Address Space(s) and Size(s) of Other Devices: _________________________________________________ _________________________________________________ _________________________________________________ _________________________________________________ • VXI Interrupt Level(s) of Other Devices: __________________________________
Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: VXI-MXI User Manual Edition Date: October 1993 Part Number: 320222-01 Please comment on the completeness, clarity, and organization of the manual. If you find errors in the manual, please record the page numbers and describe the errors. Thank you for your help.
Glossary ___________________________________________________ Prefix Meaning Value nµmKMg- nanomicromillikilomegagiga- 10-9 10-6 10-3 103 106 109 Symbols ° degrees ohms % percent ± plus or minus A A amperes A16 Space VXIbus address space equivalent to the VME 64 KB short address space. In VXI, the upper 16 KB of A16 space is allocated for use by VXI devices configuration registers. This 16 KB region is referred to as VXI Configuration space.
Glossary Address Modifier One of six signals in the VMEbus specification used by VMEbus masters to indicate the address space and mode (supervisory/nonprivileged, data/ program/block) in which a data transfer is to take place. Address Space A set of 2n memory locations differentiated from other such sets in VXI/VMEbus systems by six addressing lines known as address modifiers. n is the number of address lines required to uniquely specify a byte location in a given space.
Glossary Block-mode Transfer An uninterrupted transfer of data elements in which the master sources only the first address at the beginning of the cycle. The slave is then responsible for incrementing the address on subsequent transfers so that the next element is transferred to or from the proper storage location. In VME, the data transfer may have no more than 256 elements; MXI does not have this restriction.
Glossary Configuration Registers A set of registers through which the system can identify a module device requirements. In order to support automatic system and memory configuration, the VXIbus specification requires that all VXIbus devices h ave a set of such registers, all accessible from the P1 connector on the VMEbus. Configuration Space The upper 16 KB of A16 space in which the configuration registers for VXI and MXIbus devices exist.
Glossary Dynamically Configured Device A device that has its logical address assigned by the Resource Manager. A VXI device initially responds at Logical Address 255 when its MODID line is asserted. A MXIbus device responds at Logical Address 255 during a priority select cycle. The Resource Manager subsequently assigns it a new logical address, which the device responds to until powered down. The VXI-MXI cannot be dynamically configured.
Glossary I IACK Interrupt Acknowledge IC Integrated Circuit IEEE Institute of Electrical and Electronics Engineers IEEE 1014 The VME specification. in. inches I/O input/output; the techniques, media, and devices used to achieve communication between entities.
Glossary M MB megabytes of memory m meters Mainframe Extender A device such as the VXI-MXI that interfaces a VXIbus mainframe to an interconnect bus. It routes bus transactions from the VXIbus to the interconnect bus or vice versa. A mainframe extender has a set of registers that defines the routing mechanisms for data transfers, interrupts, triggers, and utility bus signals, and has optional VXIbus Slot 0 capability.
Glossary N Nonprivileged Access One of the defined types of VMEbus data transfers; indicated by certain address modifier codes. Each of the defined VMEbus address spaces has a defined nonprivileged access mode. Non-Slot 0 Device A device configured for installation in any slot in a VXIbus mainframe other than Slot 0. Installing such a device into Slot 0 can damage the device, the VXIbus backplane, or both. The VXI-MXI can be configured as either a Slot 0 device or a Non-Slot 0 device.
Glossary Resource Manager A Message-Based Commander located at Logical Address 0, which provides configuration management services such as address map configuration, Commander and Servant mappings, and self-test and diagnostic management. Response A signal or interrupt generated by a device to notify another device of an asynchronous event. Responses contain the information in the Response register of a sender. RM See Resource Manager.
Glossary SMB Sub-miniature BNC; a miniature connector for coaxial cable connections. Soft Reset Occurs when the RESET bit in the VXIbus Control Register of the VXI-MXI is set. A soft reset clears signals that are asserted by bits in the configuration registers but does not clear configuration information stored in the configuration registers. Start/Stop Protocol A one-line, multiple-device protocol which can be sourced only by the VXI Slot 0 device and sensed by any other device on the VXI backplane.
Glossary TERMPWR Termination Power; 3.4 VDC for the MXIbus. Trigger Either TTL or ECL lines used for intermodule communication. TTL Transistor-Transistor Logic V V volts VDC volts direct current VMEbus Versa Module Eurocard or IEEE 1014; the IEEE Standard for a Versatile Backplane Bus.
Index definition, 2-7 description, 4-22 example, 4-23 format CMODE bit cleared, 4-22 CMODE bit set, 4-24 theory of operation, 6-6 A32BASE[7-0] bit, 4-23 A32DIR bit, 4-22, 4-23 A32EN bit, 4-22, 4-23 A32HIGH[7-0] bit, 4-24 A32LOW[7-0] bit, 4-24 A32SIZE[2-0] bit, 4-23 ACCDIR bit, 4-7 ACFAIL bit, 4-47 ACFAIL signal, 2-5, 6-3 ACFAILIE bit, 4-47 ACFAILIN bit, 4-29 ACFAILINT bit, 4-46 ACFAILOUT bit, 4-29 ADDR bit, 4-4 arbiter circuitry, VMEbus, 2-5, 6-2 arbitration mode. See interlocked arbitration mode.
Index A32EN, 4-22, 4-23 A32HIGH[7-0], 4-24 A32LOW[7-0], 4-24 A32SIZE[2-0], 4-23 ACCDIR, 4-7 ACFAIL, 4-47 ACFAILIE, 4-47 ACFAILIN, 4-29 ACFAILINT, 4-46 ACFAILOUT, 4-29 ADDR, 4-4 ASIE, 4-44 ASINT*, 4-44 BKOFF, 4-46 BKOFFIE, 4-46 BOFFCLR, 4-35 CMODE, 4-32 DEVCLASS, 4-4 DIRQ[7-1], 4-47 DRVECL0, 4-40 DRVECL1, 4-40 DSYSFAIL, 4-33 DSYSRST, 4-34 DTRIG[7-0], 4-39 ECL0DIR, 4-33 ECL0EN, 4-33 ECL1DIR, 4-32 ECL1EN, 4-32 ECLSTAT0, 4-43 ECLSTAT1, 4-43 EDTYPE, 4-7 EINT[7-1]DIR, 4-26 EINT[7-1]EN, 4-26 ETOEN, 4-43 ETRG[7-0]
Index BTO. See VME BTO chain position; VME BTO circuitry.
Index environmental specifications, A-2 to A-3 equipment, optional, 1-6 to 1-7 ETOEN bit, 4-43 ETRG[7-0]DIR bit, 4-27 ETRG[7-0]EN bit, 4-27 ETRIG bit, 4-44 EXT CLK connector, 6-2 EXT CLK SMB input/output configuration, 3-20 Extended P2 ECL Trigger Line Support (1) bit, 4-28 Extended P3 ECL Trigger Line Support (1) bit, 4-28 Extended TTL Trigger Line Support (0) bit, 4-28 Extended Utility Line Support (0) bit, 4-28 unpacking the VXI-MXI interface module, 1-7 interlocked arbitration mode, configuration, 3-1
Index jumpers and switches CLK10 source signal options, 3-19 EXT CLK SMB input/output, 3-20 factory default settings VXI-MXI with INTX, 3-3 VXI-MXI without INTX, 3-2 interlocked arbitration mode, 3-14 INTX CLK10 mapping switches, 3-21 to 3-22 logical address, 3-6 to 3-7 MXIbus fairness option, 3-17 MXIbus System Controller, 3-15 MXIbus System Controller timeout, 3-16 non-Slot 0 selection, 3-5 reset signal settings, 3-23 Slot 0 settings, 3-4 trigger input termination, 3-22 VME BTO chain position, 3-10 to 3-
Index connector description, D-1 to D-2 definition, 1-4 limit for daisy-chained devices, 3-29 mapping, 1-4 signal assignments, D-1 signal groupings, D-2 system power cycling requirements, 3-30 to 3-31 termination networks, 3-24 to 3-25 MXIbus defined registers configuration registers, 2-7, 6-6 Drive Triggers/Read LA Register, 4-39 to 4-40, 6-2 Interrupt Status/Control Register, 4-45 to 4-47 IRQ Acknowledge Registers, 4-51 MXIbus IRQ Configuration Register, 4-37 to 4-38 MXIbus Lock Register, 4-36 MXIbus Sta
Index requester and arbiter circuitry, VMEbus, 2-5, 6-2 RESET bit, 4-8 reset signal, configuration, 3-23 resets hard and soft resets for registers, 4-1 INTX daughter card control, 6-9 RM operation. See multiframe RM operation.
Index SUBCLASS bit, 4-30 Subclass Register, 4-30 switches. See jumpers and switches. Synchronous protocol, 6-3 SYSFAIL bit, 4-46 SYSFAIL signal, 2-5, 6-3 SYSFAILIE bit, 4-46 SYSFAILIN bit, 4-29 SYSFAILINT bit, 4-47 SYSFAILOUT bit, 4-29 SYSFIN bit, 4-37 SYSFOUT bit, 4-37 SYSRESET signal, 2-5, 6-3 SYSRSTIN bit, 4-29 SYSRSTOUT bit, 4-29 System Controller. See MXIbus System Controller; VMEbus System Controller. system logical address map configuration. See logical address map configuration.
Index signals list of signals, 2-1 to 2-2 signals supplied by VXI-MXI, 1-4 to 1-5 VMEbus Data Transfer Bus Arbiter (PRI ARBITER), 3-5 VMEbus Data Transfer Bus (DTB), 3-7 VMEbus System Controller, 3-5 VMEbus timeout. See VME BTO chain position; VME BTO circuitry. VMEbus transceivers address and address modifier transceivers, 2-5, 6-1 control signal transceivers, 2-5, 6-2 data transceivers, 2-5, 6-1 VXI-MXI interface module. See also INTX daughter card.
