VXI-MXI-2 User Manual August 1996 Edition Part Number 371692A-01 © Copyright 1995, 1996 National Instruments Corporation. All Rights Reserved.
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Important Information Warranty The VXI-MXI-2 and VXI-MXI-2/B are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
FCC/DOC Radio Frequency Interference Class A Compliance This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the instructions in this manual, may cause interference to radio and television reception. Classification requirements are the same for the Federal Communications Commission (FCC) and the Canadian Department of Communications (DOC).
Table of Contents About This Manual Organization of This Manual........................................................................................xiii Conventions Used in This Manual................................................................................xv How to Use This Manual..............................................................................................xvi Related Documentation ................................................................................................
Table of Contents Configuration EEPROM ................................................................................3-15 Onboard DRAM .............................................................................................3-17 Install the VXI-MXI-2..................................................................................................3-19 Connect the MXIbus Cable ..........................................................................................
Table of Contents VXIbus Trigger Mode Select Register (VTMSR)..........................................5-36 VXIbus Interrupt Status Register (VISTR) ....................................................5-37 VXIbus Interrupt Control Register (VICTR) .................................................5-39 VXIbus Status ID Register (VSIDR) .............................................................5-41 VXI-MXI-2 Trigger Control Register (VMTCR) ..........................................
Table of Contents Chapter 7 VXIplug&play for the VXI-MXI-2 VXI-MXI-2 VXIplug&play Soft Front Panel ..............................................................7-1 Installing the Soft Front Panel........................................................................7-1 Using the Soft Front Panel .............................................................................7-2 Board Settings ................................................................................................
Table of Contents VMEbus Requester ........................................................................................B-7 Request Level...................................................................................B-7 Fair Request .....................................................................................B-7 MXIbus Timer Limit ......................................................................................B-8 MXIbus Fair Requester and MXIbus Parity Checking ........................
Table of Contents Appendix F DMA Programming Examples Overview of Programming Examples ..........................................................................F-1 Parameter Descriptions ..................................................................................F-2 Example 1: DMA Operation without Interrupt............................................................F-2 Example 2: DMA Operation with Interrupt.................................................................
Table of Contents Figure 4-8. Figure 4-9. Figure 4-10. Figure 4-11. Figure 4-12. SMB Trigger Input Termination............................................................4-12 MXIbus Termination .............................................................................4-13 EEPROM Operation..............................................................................4-15 SIMM Size Configuration .....................................................................
Table of Contents Figure C-1. Figure C-2 Figure C-3. Figure C-4. Figure C-5. Figure C-6. C-Size VXI-MXI-2 Front Panel Layout................................................C-2 VXI-MXI-2/B Front Panel Layout........................................................C-3 MXI-2 Connector ..................................................................................C-4 EXT CLK Connector.............................................................................C-6 TRG OUT Connector ..........................
About This Manual The VXI-MXI-2 User Manual describes the functional, physical, and electrical aspects of the VXI-MXI-2 and VXI-MXI-2/B and contains information concerning its operation and programming. This manual uses the term VXI-MXI-2 to describe both the C-size VXI-MXI-2 and the B-size VXI-MXI-2/B except where it is necessary to specify between the two models.
About This Manual VXI-MXI-2 User Manual • Chapter 7, VXIplug&play for the VXI-MXI-2, describes the contents of the VXIplug&play disk that came with your VXI-MXI-2 kit. The disk contains a VXIplug&play soft front panel and a VXIplug&play knowledge base file. • Appendix A, Specifications, lists various module specifications of the VXI-MXI-2, such as physical dimensions and power requirements.
About This Manual • Appendix H, Customer Communication, contains forms you can use to request help from National Instruments or to comment on our products and manuals. • The Glossary contains an alphabetical list and description of terms used in this manual, including abbreviations, acronyms, metric prefixes, and symbols. • The Index contains an alphabetical list of key terms and topics in this manual, including the page where you can find each one.
About This Manual How to Use This Manual If you will be installing your VXI-MXI-2 into a system with a VXIbus Multiframe Resource Manager, you only need to read Chapters 1, 2, and 3 of this manual (or Chapters 1, 2, and 4 if you have a VXI-MXI-2/B). If you have more than two VXI-MXI-2 modules extending your system, you will find useful system configuration information in Chapter 6. Appendix E is a quick reference for users who have a system containing two mainframes linked by VXI-MXI-2 modules.
Chapter 1 Introduction This chapter describes the VXI-MXI-2 and VXI-MXI-2/B, lists what you need to get started, lists optional equipment, and introduces the concepts of MXI-2. Unless otherwise noted, the term VXI-MXI-2 refers to both the C-size VXI-MXI-2 and the B-size VXI-MXI-2/B. VXI-MXI-2 Overview The VXI-MXI-2 interface is a C-size extended class mainframe extender for the VXIbus (VMEbus Extensions for Instrumentation). The VXI-MXI-2/B is a B-size extended class mainframe extender for the VXIbus.
Chapter 1 Introduction MXI-2 cable VXIplug&play diskette MXI-2 Description MXI-2 is the second generation of the National Instruments MXIbus product line. The MXIbus is a general-purpose, 32-bit, multimaster system bus on a cable. MXI-2 expands the number of signals on a standard MXI cable by including all VXIbus interrupts, VXIbus triggers, VXIbus CLK10, and all of the VMEbus utility bus signals (SYSFAIL*, SYSRESET*, and ACFAIL*).
Chapter 1 Introduction The VXI-MXI-2 converts A32, A24, A16, D64, D32, D16, and D08(EO) VXIbus bus cycles into MXIbus bus cycles and vice versa. The VXI-MXI-2 has four address windows that map into and out of the VXIbus mainframe. These four windows represent the three VMEbus address spaces (A32, A24, and A16) plus a dedicated window for mapping the VXIbus configuration space (the upper 16 KB of A16 space).
Chapter 1 Introduction • Can extend VMEbus interrupt levels, utility signals, VXIbus TTL triggers, and CLK10 to MXIbus • Can source or sense VXIbus TTL and P2 ECL trigger lines • Supports dynamic configuration of VXIbus devices • Can operate in either one of two modes: parallel or interlocked • Allows for optional or user-installable onboard DRAM up to 64 MB, which can be shared with the VXIbus and MXIbus • Conforms to VXI-6, the VXIbus Mainframe Extender Specification • Conforms to the MXI-2
Chapter 1 – • Introduction Responds to D16 or D32 IACK cycles VXIbus Slot 0 functions: – 10 MHz clock – MODID register The VXI-MXI-2 does not have support for the serial clock driver or power monitor VMEbus modules. All integrated circuit drivers and receivers used on the VXI-MXI-2 meet the requirements of both the VXIbus specification and the MXIbus specification.
Chapter 1 Introduction VXI-MXI-2 User Manual • Type M3 MXI-2 Cables— Right-angle point connector to right-angle daisy-chain connector; available in lengths of 1, 2, 4, 8, or 20 m • Type M4 MXI-2 Cables— Straight-point connector to reverse right-angle daisy-chain connector; available in lengths of 1, 2, 4, 8, or 20 m • Onboard DRAM options of 4, 8, 16, 32, or 64 MB 1-6 © National Instruments Corporation
Chapter Functional Overview 2 This chapter contains functional descriptions of each major logic block on the VXI-MXI-2. VXI-MXI-2 Functional Description In the simplest terms, you can think of the VXI-MXI-2 as a bus translator that converts VXIbus signals into appropriate MXIbus signals. From the perspective of the MXIbus, the VXI-MXI-2 implements a MXIbus interface to communicate with other MXIbus devices. From the perspective of the VXIbus, the VXI-MXI-2 is an interface to the outside world.
Chapter 2 Functional Overview DMA Controller 2 DMA Controller 1 VXIbus Slot 0 Functions VMEbus Control Signals Xcvrs BERR VMEbus Bus Timeout Unit VMEbus Master State Machine MXI-2 Master State Machine VMEbus Slave State Machine MXI-2 Slave State Machine MXI-2 System Controller Functions MXI-2 Control Signals Xcvrs A24/A32 Decoder MXI-2 Parity Check and Generation Logical Address Decoder A[31-1] AM[5-0] VMEbus Address and Address Modifier Xcvrs A32 Window PAR AD[31-0] MXI-2 Address/ Data
Chapter 2 Functional Overview • VXIbus Slot 0 Functions When the VXI-MXI-2 is installed in slot 0 of a VXIbus mainframe it assumes the Slot 0 responsibilities defined in the VXIbus specification. These are the VMEbus 16 MHz system clock driver, VMEbus arbiter, VMEbus IACK daisy-chain driver, VXIbus CLK10 driver, and VXIbus MODID register. All of these functions are disabled when the VXI-MXI-2 is not acting as the VXIbus Slot 0 device.
Chapter 2 Functional Overview • MXI-2 Master State Machine This state machine generates MXIbus master data transfer cycles when directed to do so by the VMEbus slave state machine, thus allowing VMEbus cycles to map to the MXIbus. This state machine will also generate MXIbus master data transfer cycles when instructed to do so by one of the DMA controllers. The VXI-MXI-2 can generate D64, D32, D16, and D08(EO) single, block, RMW, and synchronous burst cycles on the MXIbus in A32 and A24 space.
Chapter 2 Functional Overview • MXI-2 Slave State Machine This state machine monitors the output of the address decoders and extender window decoders and responds to MXIbus cycles that are intended for the VXI-MXI-2. Cycles that map to the Logical Address decoder access the VXI-MXI-2 registers, while cycles that map to the A24/A32 decoder access either the VXI-MXI-2 registers or the onboard DRAM SIMMs.
Chapter 2 Functional Overview • MXI-2 Parity Check and Generation The MXI-2 parity check/generation circuitry checks for even parity at any time that the VXI-MXI-2 is receiving the AD[31–0] signals. If parity is not even, the appropriate MXI-2 state machine is signaled.
Chapter 2 Functional Overview • VXI-MXI-2 Registers This logic block represents all registers on the VXI-MXI-2. The registers are accessible from either the VXIbus or the MXIbus. All registers are available in the first 4 KB of the VXI-MXI-2 A24/A32 memory space, while a subset is accessible in the VXI-MXI-2 VXIbus A16 configuration area. • Onboard DRAM SIMMs This logic block represents the two DRAM SIMM sockets on the VXI-MXI-2.
Chapter VXI-MXI-2 Configuration and Installation 3 This chapter contains the instructions to configure and install the C-size VXI-MXI-2 module. If you have a VXI-MXI-2/B, see Chapter 4, VXI-MXI-2/B Configuration and Installation. Some features of the VXI-MXI-2 are not configurable with onboard switches or jumpers but are instead programmable. Refer to Chapter 7, VXIplug&play for the VXI-MXI-2, or Appendix B, Programmable Configurations, for a description of the programmable features.
U43 S6 S5 3-2 10 11 12 Termination for External Trigger Input SMB CLK10 Direction 50 Termination for SMB CLK10 (Effective only when S3 is set to "IN") 50 On NATIONAL INSTRUMENTS SMB CLK10 Output Polarity (Effective only when S3 is set to "OUT") In On Off Out Off 7 8 9 S2 S3 S4 S8 S9 S7 S5 NON-INVERTED INVERTED Turn off power to instruments and cables before installing or removing any modules.
Chapter 3 VXI-MXI-2 Configuration and Installation Removing the Metal Enclosure The VXI-MXI-2 is housed in a metal enclosure to improve EMC performance and to provide easy handling. Because the enclosure includes cutouts to facilitate changes to the switch and jumper settings, it should not be necessary to remove it under normal circumstances. However, it is necessary to remove the enclosure if you want to change the amount of DRAM installed on the VXI-MXI-2.
Chapter 3 VXI-MXI-2 Configuration and Installation You can change the logical address of the VXI-MXI-2 by changing the setting of the 8-bit DIP switch labeled LOGICAL ADDRESS SWITCH (location designator U43) on the panel. The down position of the DIP switch corresponds to a logic value of 0 and the up position corresponds to a logic value of 1. Verify that the VXI-MXI-2 does not have the same logical address as any other statically configured VXIbus device in your system.
Chapter 3 VXI-MXI-2 Configuration and Installation VXIbus Slot 0/Non-Slot 0 The VXI-MXI-2 is configured at the factory to automatically detect if it is installed in Slot 0 of a VXIbus mainframe. With automatic Slot 0 detection, you can install the VXI-MXI-2 into any VXIbus slot. You can manually configure the VXI-MXI-2 for either Slot 0 or Non-Slot 0 operation by defeating the automatic-detection circuitry.
Chapter 3 VXI-MXI-2 Configuration and Installation When the VXI-MXI-2 is installed in Slot 0, it becomes the VMEbus System Controller. In this role, it has VMEbus Data Transfer Bus Arbiter circuitry that accepts bus requests on all four VMEbus request levels, prioritizes the requests, and grants the bus to the highest priority requester. As VMEbus System Controller, the VXI-MXI-2 also drives the 16 MHz VMEbus system clock by an onboard 16 MHz oscillator.
Chapter 3 VXI-MXI-2 Configuration and Installation S8 S8 S9 No S9 Yes No VXI-MXI to left VXI-MXI to left VXI-MXI to right VXI-MXI to right Yes b. Leftmost VXI-MXI-2 in Mainframe a. Single VXI-MXI-2 in Mainframe (Default) S8 S8 S9 No S9 Yes No VXI-MXI to left VXI-MXI to left VXI-MXI to right VXI-MXI to right c.VXI-MXI-2 between Two Others Yes d. Rightmost VXI-MXI-2 in Mainframe Figure 3-4.
Chapter 3 VXI-MXI-2 Configuration and Installation From onboard oscillator W3 From SMB (S3 must be set to "IN") From MXIbus a. CLK10 Generated from Onboard Oscillator (Default) From onboard oscillator From SMB (S3 must be set to "IN") In SMB CLK10 Direction W3 S3 Out From MXIbus b. CLK10 Generated from SMB From onboard oscillator From SMB (S3 must be set to "IN") Receive CLK10 from MXIbus W3 From MXIbus S7 c. CLK10 Generated from MXIbus Figure 3-5.
Chapter 3 VXI-MXI-2 Configuration and Installation The VXI-MXI-2 can also be configured to drive the external CLK SMB signal from the VXIbus CLK10 signal. Switch S3 controls whether the VXI-MXI-2 drives or receives the external CLK SMB signal. If you change the S3 setting to drive CLK10 out the external CLK10 SMB connector, do not set the W3 jumper to receive the SMB CLK10 signal; instead use the settings shown in either Figure 3-5a or Figure 3-5c as appropriate.
Chapter 3 VXI-MXI-2 Configuration and Installation S2 Off S3 Out S4 Off On 50 Ω Termination for External Trigger Input In SMB CLK10 Direction On 50 Ω Termination for SMB CLK10 (Effective only when S3 is set to "IN") SMB CLK10 Output Polarity (Effective only when S3 is set to "OUT") S5 NON-INVERTED INVERTED a.
Chapter 3 VXI-MXI-2 Configuration and Installation The VXI-MXI-2 can also drive or receive the MXIbus CLK10 signal. Switch S7 controls whether the VXI-MXI-2 drives MXIbus CLK10 from the VXIbus CLK10 or receives MXIbus CLK10. As shown earlier in Figure 3-5c, if W3 is configured to use the MXIbus CLK10 to generate the VXIbus CLK10 signal, switch S7 must be configured to receive MXIbus CLK10. This is shown again in Figure 3-7a below.
Chapter 3 VXI-MXI-2 Configuration and Installation Trigger Input Termination You can use switch S2 to terminate the external trigger input SMB with 50 Ω. Figure 3-8a shows the default setting for a nonterminated trigger input SMB. Use the setting of Figure 3-8b to terminate the trigger input SMB. Switch S2 is located above switches S3, S4, and S5, which have no effect on this configuration.
Chapter 3 VXI-MXI-2 Configuration and Installation MXIbus Termination The first and last MXIbus devices connected to the MXIbus—whether it is a single MXI-2 cable or daisy-chained MXI-2 cables—must terminate the MXIbus. Any MXIbus devices in the middle of a MXIbus daisy chain must not terminate the MXIbus. The VXI-MXI-2 automatically senses whether it is at either end of the MXIbus cable to terminate the MXIbus. You can manually control MXIbus termination by defeating the automatic circuitry.
Chapter 3 VXI-MXI-2 Configuration and Installation U35 No No Yes Yes 1 2 3 4 Restore Factory Configuration Change Factory Configuration Automatic MXIbus Termination Terminate MXIbus Yes Yes No No a. Automatic MXIbus Termination (Default) 1 2 3 4 No No Yes Yes Yes Yes No No 1 2 3 4 U35 Restore Factory Configuration Change Factory Configuration Automatic MXIbus Termination Terminate MXIbus Yes Yes No No b.
Chapter 3 VXI-MXI-2 Configuration and Installation Configuration EEPROM The VXI-MXI-2 has an onboard EEPROM, which stores default register values that are loaded at power-on. The EEPROM is divided into two halves—a factory-configuration half, and a user-configuration half. Both halves were factory configured with the same configuration values so you can modify the user-configurable half, while the factoryconfigured half stores a back-up of the factory settings.
Chapter 3 VXI-MXI-2 Configuration and Installation U35 No No Yes Yes 1 2 3 4 Restore Factory Configuration Change Factory Configuration Automatic MXIbus Termination Terminate MXIbus Yes Yes No No a. Boot from User Configuration (Factory Configuration Protected) (Default) U35 No No Yes Yes 1 2 3 4 Restore Factory Configuration Change Factory Configuration Automatic MXIbus Termination Terminate MXIbus Yes Yes No No b.
Chapter 3 VXI-MXI-2 Configuration and Installation Onboard DRAM The VXI-MXI-2 can accommodate up to two 1.35 in. DRAM SIMMs. Table 3-1 lists the SIMMS you can use. You can use 32-bit or 36-bit SIMMS since DRAM parity is not required. Because the VXI-MXI-2 supports only one organization at a time, all SIMMs installed must be of the same type. Use Bank 0 first when installing the SIMMs. This allows you to install up to 64 MB. The VXI-MXI-2 supports DRAM speeds of 80 ns or faster.
Chapter 3 VXI-MXI-2 Configuration and Installation Table 3-1.
Chapter 3 VXI-MXI-2 Configuration and Installation Install the VXI-MXI-2 This section contains general installation instructions for the VXI-MXI-2. Consult the user manual or technical reference manual of your VXIbus mainframe for specific instructions and warnings. 1. Warning: Warning: Plug in your mainframe before installing the VXI-MXI-2. The power cord grounds the mainframe and protects it from electrical damage while you are installing the module.
Chapter 3 VXI-MXI-2 Configuration and Installation Connect the MXIbus Cable There are two basic types of MXI-2 cables. MXI-2 cables can have either a single connector on each end or a single connector on one end and a double connector on the other end. Connect the labeled end of the cable to the MXI-2 device that will be the MXIbus System Controller. Connect the other end of the cable to the other device. Be sure to tighten the screw locks to ensure proper pin connection.
Chapter VXI-MXI-2/B Configuration and Installation 4 This chapter contains the instructions to configure and install the VXI-MXI-2/B module. If you have a C-size VXI-MXI-2, see Chapter 3, VXI-MXI-2 Configuration and Installation. Some features of the VXI-MXI-2/B are not configurable with onboard switches or jumpers but are instead programmable. Refer to Chapter 7, VXIplug&play for the VXI-MXI-2, or Appendix B, Programmable Configurations, for a description of the programmable features.
Chapter 4 VXI-MXI-2/B Configuration and Installation 6 5 7 8 9 4 3 2 1 10 16 15 1 2 3 4 S7 S6 S5 S3 5 6 7 8 S2 W3 W1 U21 14 13 9 10 11 12 12 W2 S1 U20 DRAM 11 13 14 15 16 Serial Number DRAM Product Name Assembly Number Figure 4-1.
Chapter 4 VXI-MXI-2/B Configuration and Installation VXIbus Logical Address Each device in a VXIbus/MXIbus system is assigned a unique number between 0 and 254. This 8-bit number, called the logical address, defines the base address for the VXI configuration registers located on the device. With unique logical addresses, each VXIbus device in the system is assigned 64 bytes of configuration space in the upper 16 KB of A16 space. Logical address 0 is reserved for the Resource Manager in the VXIbus system.
Chapter 4 VXI-MXI-2/B Configuration and Installation Figure 4-2 shows switch settings for logical address hex 1 and C0. 2 3 4 5 6 7 8 U20 1 a. Switch Set to Logical Address 1 (Default) 2 3 4 5 6 7 8 U20 1 b. Switch Set to Logical Address Hex C0 Figure 4-2.
Chapter 4 VXI-MXI-2/B Configuration and Installation VXIbus Slot 0/Non-Slot 0 The VXI-MXI-2/B is configured at the factory to automatically detect if it is installed in Slot 0 of a VXIbus mainframe. With automatic Slot 0 detection, you can install the VXI-MXI-2/B into any VXIbus slot. You can manually configure the VXI-MXI-2/B for either Slot 0 or Non-Slot 0 operation by defeating the automatic-detection circuitry.
Chapter 4 VXI-MXI-2/B Configuration and Installation When the VXI-MXI-2/B is installed in Slot 0, it becomes the VMEbus System Controller. In this role, it has VMEbus Data Transfer Bus Arbiter circuitry that accepts bus requests on all four VMEbus request levels, prioritizes the requests, and grants the bus to the highest priority requester. As VMEbus System Controller, the VXI-MXI-2/B also drives the 16 MHz VMEbus system clock by an onboard 16 MHz oscillator.
Chapter 4 VXI-MXI-2/B Configuration and Installation W2 W2 A5 A5 C5 C5 C30 C30 NC NC a. Single VXI-MXI-2/B in Mainframe (Default) b. Leftmost VXI-MXI-2/B in Mainframe W2 W2 A5 A5 C5 C5 C30 C30 NC NC c. VXI-MXI-2/B Between Two Others d. Rightmost VXI-MXI-2/B in Mainframe Figure 4-4. VXIbus Local Bus Configuration VXIbus CLK10 Routing When the VXI-MXI-2/B is installed in Slot 0 of your mainframe, it supplies the VXIbus CLK10 signal.
Chapter 4 VXI-MXI-2/B Configuration and Installation W1 ON BRD SMB MXI a. CLK10 Generated from Onboard Oscillator (Default) DIR ON BRD CLK10 SMB S7 ( = OUT) W1 MXI b. CLK10 Generated from SMB MBCLK10 OUT S1 W1 ON BRD IN SMB MXI c. CLK10 Generated from MXIbus Figure 4-5.
Chapter 4 VXI-MXI-2/B Configuration and Installation The VXI-MXI-2/B can also be configured to drive the external CLK SMB signal from the VXIbus CLK10 signal. Switch S7 controls whether the VXI-MXI-2/B drives or receives the external CLK SMB signal. If you change the S7 setting to drive CLK10 out the external CLK10 SMB connector, do not set the W1 jumper to receive the SMB CLK10 signal; instead use the settings shown in either Figure 4-5a or Figure 4-5c as appropriate.
Chapter 4 VXI-MXI-2/B Configuration and Installation ( = OUT) CLK10 ( = NO) ( = NO) DIR TERM CLK10 TERM TRIGIN S5 S3 S6 S7 CLK10 POL ( = INVERT) a. Drive Inverted External CLK SMB (Default) ( = OUT) CLK10 ( = NO) ( = NO) DIR TERM CLK10 TERM TRIGIN S5 S3 S6 S7 CLK10 POL ( = INVERT) b. Drive Non-Inverted External CLK SMB ( = OUT) CLK10 ( = NO) ( = NO) DIR TERM CLK10 TERM TRIGIN S5 S3 S6 S7 CLK10 POL ( = INVERT) c.
Chapter 4 VXI-MXI-2/B Configuration and Installation The VXI-MXI-2/B can also drive or receive the MXIbus CLK10 signal. Switch S1 controls whether the VXI-MXI-2/B drives MXIbus CLK10 from the VXIbus CLK10 or receives MXIbus CLK10. As shown earlier in Figure 4-5c, if W1 is configured to use the MXIbus CLK10 to generate the VXIbus CLK10 signal, switch S1 must be configured to receive MXIbus CLK10. This is shown again in Figure 4-7a below.
Chapter 4 VXI-MXI-2/B Configuration and Installation Trigger Input Termination You can use switch S5 to terminate the external trigger input SMB with 50 Ω. Figure 4-8a shows the default setting for a nonterminated trigger input SMB. Use the setting of Figure 4-8b to terminate the trigger input SMB. ( = NO) ( = NO) TERM TRIGIN TERM TRIGIN S5 S5 a. Non-Terminated External Trigger Input SMB (Default) b. Terminated External Trigger Input SMB with 50 Ω Figure 4-8.
Chapter 4 2 3 4 U21 1 VXI-MXI-2/B Configuration and Installation OFF a. Automatic MXIbus Termination (Default) 2 3 4 U21 1 OFF b. Terminate MXIbus (On) 2 3 4 U21 1 OFF c. Do Not Terminate MXIbus (Off) Figure 4-9.
Chapter 4 VXI-MXI-2/B Configuration and Installation Configuration EEPROM The VXI-MXI-2/B has an onboard EEPROM, which stores default register values that are loaded at power-on. The EEPROM is divided into two halves—a factory-configuration half, and a user-configuration half. Both halves were factory configured with the same configuration values so you can modify the user-configurable half, while the factoryconfigured half stores a back-up of the factory settings.
Chapter 4 2 3 4 U21 1 VXI-MXI-2/B Configuration and Installation OFF a. Boot from User Configuration (Factory Configuration Protected) (Default) 2 3 4 U21 1 OFF b. Boot from Factory Configuration (Factory Configuration Protected) 2 3 4 U21 1 OFF c. Boot from User Configuration (Factory Configuration Unprotected) 2 3 4 U21 1 OFF d. Boot from Factory Configuration (Factory Configuration Unprotected) Figure 4-10.
Chapter 4 VXI-MXI-2/B Configuration and Installation Onboard DRAM The VXI-MXI-2/B can accommodate up to two 1.35 in. DRAM SIMMs. Table 4-1 lists the SIMMS you can use. You can use 32-bit or 36-bit SIMMS since DRAM parity is not required. Because the VXI-MXI-2/B supports only one organization at a time, all SIMMs installed must be of the same type. Use Bank 0 first when installing the SIMMs. This allows you to install up to 64 MB. The VXI-MXI-2/B supports DRAM speeds of 80 ns or faster.
Chapter 4 VXI-MXI-2/B Configuration and Installation Table 4-1.
Chapter 4 VXI-MXI-2/B Configuration and Installation Install the VXI-MXI-2/B This section contains general installation instructions for the VXI-MXI-2/B. Consult the user manual or technical reference manual of your VXIbus mainframe for specific instructions and warnings. 1. Warning: To protect both yourself and the mainframe from electrical hazards, the mainframe should remain off until you are finished installing the VXI-MXI-2/B module. 2.
Chapter 4 VXI-MXI-2/B Configuration and Installation Connect the MXIbus Cable There are two basic types of MXI-2 cables. MXI-2 cables can have either a single connector on each end or a single connector on one end and a double connector on the other end. Connect the labeled end of the cable to the MXI-2 device that will be the MXIbus System Controller. Connect the other end of the cable to the other device. Be sure to tighten the screw locks to ensure proper pin connection.
Chapter Register Descriptions 5 This chapter contains detailed information on some of the VXI-MXI-2 registers, which you can use to configure and control the module’s operation. Some of these registers are a subset of the VXI-MXI-2 register set, which is accessible in VXIbus configuration (A16) space, while others are accessible only in the lower 4 KB of the VXI-MXI-2 module’s A24/A32 memory space. All registers are accessible from either the MXIbus or VXIbus.
Chapter 5 Register Descriptions to the offset of the register, while the lower eight bits are accessed during an 8-bit cycle to the offset of the register plus 1. A square is used to represent each bit. Each bit is labeled with a name inside its square. An asterisk (*) after a bit name indicates that the bit is active low. VXIbus Configuration Registers Table 5-1 is a register map of the VXI-MXI-2 register subset, which is accessible in VXIbus configuration space.
Chapter 5 Register Descriptions Table 5-1.
Chapter 5 Register Descriptions VXIbus ID Register (VIDR) VXIbus Configuration Offset: 0 (hex) Attributes: 32, 16, 8-bit accessible Read Only 15 14 13 12 11 10 9 8 DEVCLASS[1] DEVCLASS[0] ADSPC[1] ADSPC[0] MANID[11] MANID[10] MANID[9] MANID[8] 7 6 5 4 3 2 1 0 MANID[7] MANID[6] MANID[5] MANID[4] MANID[3] MANID[2] MANID[1] MANID[0] This register contains information about the VXI-MXI-2.
Chapter 5 Register Descriptions VXIbus Device Type Register (VDTR) VXIbus Configuration Offset: 2 (hex) Attributes: 16, 8-bit accessible Read Only 15 14 13 12 11 10 9 8 REQMEM[3] REQMEM[2] REQMEM[1] REQMEM[0] MODEL[11] MODEL[10] MODEL[9] MODEL[8] 7 6 5 4 3 2 1 0 MODEL[7] MODEL[6] MODEL[5] MODEL[4] MODEL[3] MODEL[2] MODEL[1] MODEL[0] This register contains information about the VXI-MXI-2 that indicates the amount of required address space and identifies the model code o
Chapter 5 Register Descriptions VXIbus Status Register (VSR) VXIbus Configuration Offset: 4 (hex) Attributes: 32, 16, 8-bit accessible Read Only 15 14 13 12 11 10 9 8 A24/A32 ACTIVE MODID* EDTYPE[3] EDTYPE[2] EDTYPE[1] EDTYPE[0] X ACCDIR 7 6 5 4 3 2 1 0 VERSION[3] VERSION[2] VERSION[1] VERSION[0] READY PASSED SFINH RESET This register contains status information about the VXI-MXI-2. This register conforms to the VXIbus specification.
Chapter 5 8 ACCDIR Register Descriptions Access Direction This bit returns a 1 when it is read from the MXIbus. When this bit is read from the VXIbus it returns a 0. 7-4 VERSION[3:0] Version Number These bits indicate the revision of the VXI-MXI-2 as shown below. These bits are not affected by hard or soft resets.
Chapter 5 Register Descriptions VXIbus Control Register (VCR) VXIbus Configuration Offset: 4 (hex) Attributes: 32, 16, 8-bit accessible Write Only 15 14 13 12 11 10 9 8 A24/A32 ENABLE X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X SFINH RESET This register provides various control bits for the VXI-MXI-2. This register conforms to the VXIbus specification.
Chapter 5 0 RESET Register Descriptions Reset Writing a 1 to this bit while the PASSED bit in the VXIbus Status Register (VSR) is clear forces the VXI-MXI-2 into the Soft Reset state. The VXI-MXI-2 cannot be put in the Soft Reset state once the PASSED bit becomes 1. When this bit is 0, the VXI-MXI-2 is in the normal operation state. This bit is cleared on a hard reset.
Chapter 5 Register Descriptions VXIbus Offset Register (VOR) VXIbus Configuration Offset: 6 (hex) Attributes: 16, 8-bit accessible Read/Write 15 14 13 12 11 10 9 8 OFFSET[15] OFFSET[14] OFFSET[13] OFFSET[12] OFFSET[11] OFFSET[10] OFFSET[9] OFFSET[8] 7 6 5 4 3 2 1 0 OFFSET[7] OFFSET[6] OFFSET[5] OFFSET[4] OFFSET[3] OFFSET[2] OFFSET[1] OFFSET[0] This register determines the base address on the VXIbus and the MXIbus at which to locate the VXI-MXI-2 module’s A24/A32 resour
Chapter 5 Register Descriptions VXIbus MODID Register (VMIDR) VXIbus Configuration Offset: 8 (hex) Attributes: 16, 8-bit accessible Read/Write 15 14 13 12 11 10 9 8 1 1 OUTEN MODID[12] MODID[11] MODID[10] MODID[9] MODID[8] 7 6 5 4 3 2 1 0 MODID[7] MODID[6] MODID[5] MODID[4] MODID[3] MODID[2] MODID[1] MODID[0] This register provides the status of the VXIbus MODID signals when the VXI-MXI-2 is installed in slot 0. It also controls the assertion of the MODID signals.
Chapter 5 Register Descriptions Extender Logical Address Window Register (VWR0) VXIbus Configuration Offset: A (hex) Attributes: 16, 8-bit accessible Read/Write 15 14 13 12 11 10 9 8 0 LAEN LADIR 1 1 LASIZE[2] LASIZE[1] LASIZE[0] 7 6 5 4 3 2 1 0 LABASE[7] LABASE[6] LABASE[5] LABASE[4] LABASE[3] LABASE[2] LABASE[1] LABASE[0] You can use this register to control the mapping of VXIbus configuration space between the VXIbus and the MXIbus.
Chapter 5 13 LADIR Register Descriptions Extender Logical Address Window Direction When this bit is set, the address range defined by LASIZE[2:0] and LABASE[7:0] applies to MXIbus cycles that are mapped in to VXIbus cycles (inward cycles). When this bit is cleared, the range applies to VXIbus cycles that are mapped out to MXIbus cycles (outward cycles). The complement of the defined range is mapped in the opposite direction. This bit is cleared by a hard reset and is not affected by a soft reset.
Chapter 5 Register Descriptions Extender A16 Window Register (VWR1) VXIbus Configuration Offset: C (hex) Attributes: 32, 16, 8-bit accessible Read/Write 15 14 13 12 11 10 9 8 0 A16EN A16DIR 1 1 A16SIZE[2] A16SIZE[1] A16SIZE[0] 7 6 5 4 3 2 1 0 A16BASE[7] A16BASE[6] A16BASE[5] A16BASE[4] A16BASE[3] A16BASE[2] A16BASE[1] A16BASE[0] You can use this register to control the mapping of VMEbus A16 space between the VXIbus and the MXIbus.
Chapter 5 13 A16DIR Register Descriptions Extender A16 Window Direction When this bit is set, the address range defined by A16SIZE[2:0] and A16BASE[7:0] applies to MXIbus cycles that are mapped in to VXIbus cycles (inward cycles). When this bit is cleared, the range applies to VXIbus cycles that are mapped out to MXIbus cycles (outward cycles). The complement of the defined range is mapped in the opposite direction. This bit is cleared by a hard reset and is not affected by a soft reset.
Chapter 5 Register Descriptions Extender A24 Window Register (VWR2) VXIbus Configuration Offset: E (hex) Attributes: 16, 8-bit accessible Read/Write 15 14 13 12 11 10 9 8 0 A24EN A24DIR 1 1 A24SIZE[2] A24SIZE[1] A24SIZE[0] 7 6 5 4 3 2 1 0 A24BASE[7] A24BASE[6] A24BASE[5] A24BASE[4] A24BASE[3] A24BASE[2] A24BASE[1] A24BASE[0] You can use this register to control the mapping of VMEbus A24 space between the VXIbus and the MXIbus.
Chapter 5 13 A24DIR Register Descriptions Extender A24 Window Direction When this bit is set, the address range defined by A24SIZE[2:0] and A24BASE[7:0] applies to MXIbus cycles that are mapped in to VXIbus cycles (inward cycles). When this bit is cleared, the range applies to VXIbus cycles that are mapped out to MXIbus cycles (outward cycles). The complement of the defined range is mapped in the opposite direction. This bit is cleared by a hard reset and is not affected by a soft reset.
Chapter 5 Register Descriptions Extender A32 Window Register (VWR3) VXIbus Configuration Offset: 10 (hex) Attributes: 16, 8-bit accessible Read/Write 15 14 13 12 11 10 9 8 0 A32EN A32DIR 1 1 A32SIZE[2] A32SIZE[1] A32SIZE[0] 7 6 5 4 3 2 1 0 A32BASE[7] A32BASE[6] A32BASE[5] A32BASE[4] A32BASE[3] A32BASE[2] A32BASE[1] A32BASE[0] You can use this register to control the mapping of VMEbus A32 space between the VXIbus and the MXIbus.
Chapter 5 13 A32DIR Register Descriptions Extender A32 Window Direction When this bit is set, the address range defined by A32SIZE[2:0] and A32BASE[7:0] applies to MXIbus cycles that are mapped in to VXIbus cycles (inward cycles). When this bit is cleared, the range applies to VXIbus cycles that are mapped out to MXIbus cycles (outward cycles). The complement of the defined range is mapped in the opposite direction. This bit is cleared by a hard reset and is not affected by a soft reset.
Chapter 5 Register Descriptions VXIbus Interrupt Configuration Register (VICR) VXIbus Configuration Offset: 12 (hex) Attributes: 16, 8-bit accessible Read/Write 15 14 13 12 11 10 9 8 0 INTEN[7] INTEN[6] INTEN[5] INTEN[4] INTEN[3] INTEN[2] INTEN[1] 7 6 5 4 3 2 1 0 0 INTDIR[7] INTDIR[6] INTDIR[5] INTDIR[4] INTDIR[3] INTDIR[2] INTDIR[1] You can use this register to control the routing of the seven VMEbus interrupt lines between the VXIbus and the MXIbus.
Chapter 5 6-0 INTDIR[7:1] Register Descriptions Interrupt Direction When the corresponding INTEN[7:1] bit is clear, these bits are ignored. When the corresponding INTEN[7:1] bit is set, these bits control the direction that the interrupt is routed. The interrupt is routed from the VXIbus to the MXIbus when its INTDIR[7:1] bit is 0 (outward), and from the MXIbus to the VXIbus when its INTDIR[7:1] bit is 1 (inward). These bits are cleared by a hard reset and are not affected by a soft reset.
Chapter 5 Register Descriptions VXIbus TTL Trigger Configuration Register (VTCR) VXIbus Configuration Offset: 14 (hex) Attributes: 16, 8-bit accessible Read/Write 15 14 13 12 11 10 9 8 TTLTRGEN[7] TTLTRGEN[6] TTLTRGEN[5] TTLTRGEN[4] TTLTRGEN[3] TTLTRGEN[2] TTLTRGEN[1] TTLTRGEN[0] 7 6 5 4 3 2 1 0 TTLTRGDIR[7] TTLTRGDIR[6] TTLTRGDIR[5] TTLTRGDIR[4] TTLTRGDIR[3] TTLTRGDIR[2] TTLTRGDIR[1] TTLTRGDIR[0] You can use this register to control the routing of the eight VXIbus TTL
Chapter 5 Register Descriptions VXIbus Utility Configuration Register (VUCR) VXIbus Configuration Offset: 18 (hex) Attributes: 16, 8-bit accessible Read/Write 15 14 13 12 11 10 9 8 TTL* ECL3* ECL2* UTIL* 1 1 1 1 7 6 5 4 3 2 1 0 1 1 ACFIN ACFOUT SFIN SFOUT SRIN SROUT This register indicates that the VXI-MXI-2 supports TTL trigger routing and VMEbus utility signal routing and does not support any ECL trigger routing.
Chapter 5 Register Descriptions 12 UTIL* Utility Signal Support This read-only bit returns a 0 to indicate that the VXI-MXI-2 supports routing of the VMEbus utility signals ACFAIL*, SYSFAIL*, and SYSRESET*. The value written to this bit is irrelevant. 11-6 1 Reserved These bits are reserved. They return 111111 (binary) when read. Write each of these bits with 1 when writing to the VUCR.
Chapter 5 1 SRIN Register Descriptions SYSRESET* In Setting this bit causes the VXI-MXI-2 to route the SYSRESET* signal from the MXIbus to the VXIbus. When this bit is clear, SYSRESET* is ignored on the MXIbus. This bit is cleared by a hard reset and is not affected by a soft reset. 0 SROUT SYSRESET* Out Setting this bit causes the VXI-MXI-2 to route the SYSRESET* signal from the VXIbus to the MXIbus. When this bit is clear, SYSRESET* is ignored on the VXIbus.
Chapter 5 Register Descriptions VXIbus Subclass Register (VSCR) VXIbus Configuration Offset: 1E (hex) Attributes: 16, 8-bit accessible Read Only 15 14 13 12 11 10 9 8 SC[15] SC[14] SC[13] SC[12] SC[11] SC[10] SC[9] SC[8] 7 6 5 4 3 2 1 0 SC[7] SC[6] SC[5] SC[4] SC[3] SC[2] SC[1] SC[0] The Subclass Register (VSCR) is used to specify the precise class of a device when it indicates with the DEVCLASS[1:0] bits in the VXIbus ID Register (VIDR) that it is an Extended Class de
Chapter 5 Register Descriptions VXI-MXI-2 Status Register (VMSR) VXIbus Configuration Offset: 20 (hex) Attributes: 16, 8-bit accessible Read Only 15 14 13 12 11 10 9 8 0 CMODE 1 POSTERR MXSCTO INTLCK DSYSFAIL FAIR 7 6 5 4 3 2 1 0 MXISC 0 0 0 SCFG MBERR 0 PARERR This VXI-MXI-2-specific register provides status bits for various operations. Bit Mnemonic Description 15 0 Reserved This bit is reserved and returns 0 when read.
Chapter 5 Register Descriptions 11 MXSCTO MXIbus System Controller Timeout Status If the VXI-MXI-2 is the MXIbus System Controller, this bit is set when the VXI-MXI-2 terminates a MXIbus cycle with a BERR due to a bus timeout. This bit is cleared by hard and soft resets and when read. 10 INTLCK Interlocked Status This bit reflects the state of the INTLCK bit in the VXI-MXI-2 Control Register (VMCR).
Chapter 5 2 MBERR Register Descriptions MXIbus Bus Error Status If this bit is set, the VXI-MXI-2 terminated the previous MXIbus transfer by driving the MXIbus BERR* line. This indicates that the cycle was terminated because of a bus error or a retry condition. This bit is cleared by hard and soft resets and on successful MXIbus accesses. 1 0 Reserved This bit is reserved and returns 0 when read.
Chapter 5 Register Descriptions VXI-MXI-2 Control Register (VMCR) VXIbus Configuration Offset: 20 (hex) Attributes: 16, 8-bit accessible Write Only 15 14 13 12 11 10 9 8 0 CMODE ECLEN[1] ECLDIR[1] ECLEN[0] ECLDIR[0] DSYSFAIL DSYSRST 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 INTLCK This VXI-MXI-2 specific register provides control bits for various operations. Bit Mnemonic Description 15 0 Reserved This bit is reserved. Write a 0 when writing to this bit.
Chapter 5 Register Descriptions maps to the MXIbus, while a MXIbus cycle out of that range maps to the VXIbus. When HIGH[7:0] = LOW[7:0] = 0, the window is disabled. When FF (hex) ≥ (HIGH[7:0] = LOW[7:0]) ≥ 80 (hex), all VXIbus addresses are mapped out to the MXIbus. When 7F (hex) ≥ (HIGH[7:0] = LOW[7:0]) > 0, all MXIbus addresses are mapped in to the VXIbus. To accommodate 8-bit devices that write to the VWRx registers, the window is not enabled until the lower byte is written.
Chapter 5 Register Descriptions 10 ECLDIR[0] ECL Trigger [0] Direction When the ECLEN[0] bit is clear, this bit is ignored. When the ECLEN[0] bit is set, this bit controls the direction in which the trigger is routed. The trigger is routed from the VXIbus to the TRG OUT SMB connector when ECLDIR[0] is 0 (outward), and from the TRG IN SMB connector to the VXIbus when ECLDIR[0] is 1 (inward). This bit is cleared by a hard reset and is not affected by a soft reset.
Chapter 5 Register Descriptions VXIbus Lock Register (VLR) VXIbus Configuration Offset: 22 (hex) Attributes: 16, 8-bit accessible Read/Write 15 14 13 12 11 10 9 8 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 LOCKED This register is used to lock the VXIbus or the MXIbus. This register performs differently depending on whether the register is accessed from the VXIbus or the MXIbus.
Chapter 5 Register Descriptions VXIbus Logical Address Register (VLAR) VXIbus Configuration Offset: 26 (hex) Attributes: 16, 8-bit accessible Read Only 15 14 13 12 11 10 9 8 TRIG[7] TRIG[6] TRIG[5] TRIG[4] TRIG[3] TRIG[2] TRIG[1] TRIG[0] 7 6 5 4 3 2 1 0 LA[7] LA[6] LA[5] LA[4] LA[3] LA[2] LA[1] LA[0] This register provides the logical address of the VXI-MXI-2. It also allows monitoring of the VXIbus TTL trigger [7:0] lines.
Chapter 5 Register Descriptions VXIbus Trigger Drive Register (VTDR) VXIbus Configuration Offset: 26 (hex) Attributes: 16, 8-bit accessible Write Only 15 14 13 12 11 10 9 8 DTTRIG[7] DTTRIG[6] DTTRIG[5] DTTRIG[4] DTTRIG[3] DTTRIG[2] DTTRIG[1] DTTRIG[0] 7 6 5 4 3 2 1 0 0 0 0 0 0 0 DETRIG[1] DETRIG[0] This register allows the VXI-MXI-2 to assert the VXIbus TTL and ECL trigger lines.
Chapter 5 Register Descriptions VXIbus Trigger Mode Select Register (VTMSR) VXIbus Configuration Offset: 28 (hex) Attributes: 16, 8-bit accessible Read Only 15 14 13 12 11 10 9 8 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 ETRIG[1] ETRIG[0] 1 1 TRGIN TRGOUT 1 1 You can use this register to monitor the VXIbus P2 ECL trigger [1:0] lines as well as the front-panel SMB connector triggers.
Chapter 5 Register Descriptions VXIbus Interrupt Status Register (VISTR) VXIbus Configuration Offset: 2A (hex) Attributes: 16, 8-bit accessible Read Only 15 14 13 12 11 10 9 8 LINT[3] LINT[2] LINT[1] AFINT BKOFF 0 SYSFAIL ACFAIL 7 6 5 4 3 2 1 0 SFINT IRQ[7] IRQ[6] IRQ[5] IRQ[4] IRQ[3] IRQ[2] IRQ[1] You can use this register to monitor the VMEbus IRQ[7:1] lines and the status of local VXI-MXI-2 interrupt conditions.
Chapter 5 Register Descriptions 10 0 Reserved This bit is reserved and returns 0 when read. 9 SYSFAIL SYSFAIL* Status This bit returns the current state of the VMEbus SYSFAIL* signal. A 1 indicates that SYSFAIL* is asserted (low), while a 0 indicates it is not asserted (high). If the SFIE bit in the VXIbus Interrupt Control Register (VICTR) is set, an interrupt is also generated when SYSFAIL* asserts. 8 ACFAIL ACFAIL* Status This bit returns the current state of the VMEbus ACFAIL* signal.
Chapter 5 Register Descriptions VXIbus Interrupt Control Register (VICTR) VXIbus Configuration Offset: 2A (hex) Attributes: 16, 8-bit accessible Write Only 15 14 13 12 11 10 9 8 LINT[3] LINT[2] LINT[1] 0 BKOFFIE 0 SFIE AFIE 7 6 5 4 3 2 1 0 0 DIRQ[7] DIRQ[6] DIRQ[5] DIRQ[4] DIRQ[3] DIRQ[2] DIRQ[1] This register allows the VXI-MXI-2 to assert the VMEbus IRQ[7:1] lines and provides enable bits for the various VXI-MXI-2 local interrupts.
Chapter 5 Register Descriptions 9 SFIE SYSFAIL* Interrupt Enable Writing a 1 to this bit enables the SFINT interrupt condition in the VXIbus Interrupt Status Register (VISTR) to assert the VMEbus IRQ[7:1] selected by LINT[3:1]. This bit is cleared by a hard reset and is not affected by a soft reset. 8 AFIE ACFAIL* Interrupt Enable Writing a 1 to this bit enables the AFINT interrupt condition in the VXIbus Interrupt Status Register (VISTR) to assert the VMEbus IRQ[7:1] selected by LINT[3:1].
Chapter 5 Register Descriptions VXIbus Status ID Register (VSIDR) VXIbus Configuration Offset: 2C (hex) Attributes: 16, 8-bit accessible Read/Write 15 14 13 12 11 10 9 8 S[15] S[14] S[13] S[12] S[11] S[10] S[9] S[8] 7 6 5 4 3 2 1 0 S[7] S[6] S[5] S[4] S[3] S[2] S[1] S[0] This register contains the Status ID value, which is returned during an interrupt acknowledge cycle for an IRQ[7:1] line that is being driven with the DIRQ[7:1] bits in the VXIbus Interrupt Control Reg
Chapter 5 Register Descriptions VXI-MXI-2 Trigger Control Register (VMTCR) VXIbus Configuration Offset: 2E (hex) Attributes: 16, 8-bit accessible Read/Write 15 14 13 12 11 10 9 8 TRIGEN[7] TRIGEN[6] TRIGEN[5] TRIGEN[4] TRIGEN[3] TRIGEN[2] TRIGEN[1] TRIGEN[0] 7 6 5 4 3 2 1 0 TRIGDIR[7] TRIGDIR[6] TRIGDIR[5] TRIGDIR[4] TRIGDIR[3] TRIGDIR[2] TRIGDIR[1] TRIGDIR[0] You can use this register to control the routing of the eight VXIbus TTL trigger lines between the VXIbus and
Chapter 5 Register Descriptions VXIbus Interrupt Acknowledge Register 1 (VIAR1) VXIbus Configuration Offset: 32 (hex) Attributes: 16, 8-bit accessible Read Only 15 14 13 12 11 10 9 8 I1[15} I1[14] I1[13] I1[12] I1[11] I1[10] I1[9] I1[8] 7 6 5 4 3 2 1 0 I1[7] I1[6] I1[5] I1[4] I1[3] I1[2] I1[1] I1[0] This register generates a VXIbus Interrupt Acknowledge (IACK) cycle for interrupt level 1 when read from the MXIbus and returns the Status ID received from the interrupter.
Chapter 5 Register Descriptions VXIbus Interrupt Acknowledge Register 2 (VIAR2) VXIbus Configuration Offset: 34 (hex) Attributes: 32, 16, 8-bit accessible Read Only 31 30 29 28 27 26 25 24 I2[31] I2[30] I2[29] I2[28] I2[27] I2[26] I2[25] I2[24] 23 22 21 20 19 18 17 16 I2[23] I2[22] I2[21] I2[20] I2[19] I2[18] I2[17] I2[16] 15 14 13 12 11 10 9 8 I2[15] I2[14] I2[13] I2[12] I2[11] I2[10] I2[9] I2[8] 7 6 5 4 3 2 1 0 I2[7] I2[6] I2[5] I2[4] I2[3
Chapter 5 Register Descriptions VXIbus Interrupt Acknowledge Register 3 (VIAR3) VXIbus Configuration Offset: 36 (hex) Attributes: 16, 8-bit accessible Read Only 15 14 13 12 11 10 9 8 I3[15] I3[14] I3[13] I3[12] I3[11] I3[10] I3[9] I3[8] 7 6 5 4 3 2 1 0 I3[7] I3[6] I3[5] I3[4] I3[3] I3[2] I3[1] I3[0] This register generates a VXIbus Interrupt Acknowledge (IACK) cycle for interrupt level 3 when read from the MXIbus and returns the Status ID received from the interrupter.
Chapter 5 Register Descriptions VXIbus Interrupt Acknowledge Register 4 (VIAR4) VXIbus Configuration Offset: 38 (hex) Attributes: 32, 16, 8-bit accessible Read Only 31 30 29 28 27 26 25 24 I4[31] I4[30] I4[29] I4[28] I4[27] I4[26] I4[25] I4[24] 23 22 21 20 19 18 17 16 I4[23] I4[22] I4[21] I4[20] I4[19] I4[18] I4[17] I4[16] 15 14 13 12 11 10 9 8 I4[15] I4[14] I4[13] I4[12] I4[11] I4[10] I4[9] I4[8] 7 6 5 4 3 2 1 0 I4[7] I4[6] I4[5] I4[4] I4[3
Chapter 5 Register Descriptions VXIbus Interrupt Acknowledge Register 5 (VIAR5) VXIbus Configuration Offset: 3A (hex) Attributes: 16, 8-bit accessible Read Only 15 14 13 12 11 10 9 8 I5[15] I5[14] I5[13] I5[12] I5[11] I5[10] I5[9] I5[8] 7 6 5 4 3 2 1 0 I5[7] I5[6] I5[5] I5[4] I5[3] I5[2] I5[1] I5[0] This register generates a VXIbus Interrupt Acknowledge (IACK) cycle for interrupt level 5 when read from the MXIbus and returns the Status ID received from the interrupter.
Chapter 5 Register Descriptions VXIbus Interrupt Acknowledge Register 6 (VIAR6) VXIbus Configuration Offset: 3C (hex) Attributes: 32, 16, 8-bit accessible Read Only 31 30 29 28 27 26 25 24 I6[31] I6[30] I6[29] I6[28] I6[27] I6[26] I6[25] I6[24] 23 22 21 20 19 18 17 16 I6[23] I6[22] I6[21] I6[20] I6[19] I6[18] I6[17] I6[16] 15 14 13 12 11 10 9 8 I6[15] I6[14] I6[13] I6[12] I6[11] I6[10] I6[9] I6[8] 7 6 5 4 3 2 1 0 I6[7] I6[6] I6[5] I6[4] I6[3
Chapter 5 Register Descriptions VXIbus Interrupt Acknowledge Register 7 (VIAR7) VXIbus Configuration Offset: 3E (hex) Attributes: 16, 8-bit accessible Read Only 15 14 13 12 11 10 9 8 I7[15] I7[14] I7[13] I7[12] I7[11] I7[10] I7[9] I7[8] 7 6 5 4 3 2 1 0 I7[7] I7[6] I7[5] I7[4] I7[3] I7[2] I7[1] I7[0] This register generates a VXIbus Interrupt Acknowledge (IACK) cycle for interrupt level 7 when read from the MXIbus and returns the Status ID received from the interrupter.
Chapter 5 Register Descriptions VXIbus A24/A32 Registers Some of the registers on the VXI-MXI-2 are accessible only within the A24 or A32 space that the Resource Manager allocates to the VXI-MXI-2. The following are register descriptions of some of these registers. See Table 5-2 for a register map of these registers. The table gives the mnemonic, offset from the base address, access type (read only, write only, or read/write), access size, and register name.
Chapter 5 Register Descriptions Table 5-2.
Chapter 5 Register Descriptions DMA Interrupt Configuration Register (DMAICR) VXIbus A24 or A32 Offset: 8 (hex) Attributes: 16, 8-bit accessible Read/Write 15 14 13 12 11 10 9 8 SID8 SIDLA 1 0 1 0 0 0 7 6 5 4 3 2 1 0 ISTAT 0 0 0 0 ILVL[2] ILVL[1] ILVL[0] This register controls aspects of the DMA interrupt that are configurable. Although the two DMA controllers are independent, they share a common interrupt condition.
Chapter 5 14 SIDLA Register Descriptions Logical Address Status/ID When the SID8 bit is set, this bit selects what information is provided during IACK cycles for the DMA interrupt. This bit should not be set when SID8 is clear. When this bit is set, the logical address of the VXI-MXI-2 is used as the Status/ID information. When this bit is clear, the contents of the DMAISIDR are used. This bit is cleared on a hard reset and is not affected by a soft reset. 13 1 Reserved This bit is reserved.
Chapter 5 Register Descriptions 6-3 0 Reserved These bits are reserved. Write each of these bits with 0 when writing the DMAICR. The value these bits return when read is meaningless. 2-0 ILVL[2:0] DMA Interrupt Level These bits select the VXIbus interrupt level that the DMA interrupt condition will assert. Write a 7 to these bits for IRQ7*, write a 6 for IRQ6*, and so on. These bits must be initialized to a value between 7 and 1 for the DMA interrupt to operate properly.
Chapter 5 Register Descriptions DMA Interrupt Enable Register (DMAIER) VXIbus A24 or A32 Offset: 12 (hex) Attributes: 16, 8-bit accessible Read/Write 15 14 13 12 11 10 9 8 0 0 0 0 DMAIEN 0 0 ENABLE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 This register enables mapping of the DMA interrupt to the VXIbus.
Chapter 5 Register Descriptions 8 ENABLE Enable Interrupt This bit controls whether the interrupt is enabled or disabled when writing to the DMAIER. Write this bit with a 1 to enable the interrupt or a 0 to disable the interrupt. The DMAIEN bit should always be written with a 1. This bit always returns a 0 when read. 7-0 0 Reserved These bits are reserved. Write each of these bits with 0 when writing the DMAIER. The value these bits return when read is meaningless.
Chapter 5 Register Descriptions DMA Interrupt Status/ID Register (DMAISIDR) VXIbus A24 or A32 Offset: 20 (hex) Attributes: 16, 8-bit accessible Read/Write 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 DMASID[7] DMASID[6] DMASID[5] DMASID[4] DMASID[3] 0 1 1 This register provides the Status/ID information during IACK cycles for the DMA interrupt.
Chapter 5 Register Descriptions 2-0 ‘011’ DMA Status/ID 2 through 0 When SID8 is clear in the DMAICR (16-bit Status/ID), these bits provide bits 10 through 8 of the Status/ID. When SID8 is set (8-bit Status/ID) and SIDLA is clear in the DMAICR, these bits provide bits 2 through 0 of the Status/ID. These bits return 011 (binary) during IACK cycles and 000 (binary) when read directly.
Chapter 5 Register Descriptions VXI-MXI-2 Status/Control Register 2 (VMSR2/VMCR2) VXIbus A24 or A32 Offset: 758 (hex) Attributes: 32, 16, 8-bit accessible Read/Write 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 IOCONFIG 0 0 0 0 0 0 1 This register enables access to the VXI-MXI-2 onboard EEPROM.
Chapter 5 Register Descriptions 6-1 0 Reserved These bits are reserved. Write these bits with 0 when writing to the VMCR2. 0 1 Reserved This bit is reserved. Write this bit with 1 when writing to the VMCR2.
Chapter 5 Register Descriptions Shared MXIbus Status/Control Register (SMSR/SMCR) VXIbus A24 or A32 Offset: C40 (hex) Attributes: 32, 16, 8-bit accessible Read/Write 31 30 29 28 27 26 25 24 0 0 DMA2MBS DMA1MBS DMAMB S/N* 0 0 0 23 22 21 20 19 18 17 16 1 1 FAIR 0 0 PAREN 0 1 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 0 0 0 0 MBTO[3] MBTO[2] MBTO[1] MBTO[0] This register provides control bits for the configurable features of the
Chapter 5 Register Descriptions Notice that synchronous MXIbus burst cycles cannot be used for the source or destination of a DMA operation when both are located on the MXIbus. In such a case, you must either program this bit to use normal MXIbus block cycles, or program the DMA Source Configuration Register 2 (SCR2) and the DMA Destination Configuration Register 2 (DCR2) to both use single (non-block) cycles by clearing the BLOCKEN bit.
Chapter 5 20-19 0 Register Descriptions Reserved These bits are reserved. Write these bits with 0 when writing to the SMCR. 18 PAREN MXIbus Parity Enable Setting this bit enables the checking of MXIbus parity. When this bit is clear, the VXI-MXI-2 does not check MXIbus parity. Refer to Chapter 7, VXIplug&play for the VXI-MXI-2, or Appendix B, Programmable Configurations, for more information on MXIbus parity checking.
Chapter 5 Register Descriptions The following table lists the values to write to these bits for all possible times. Refer to Chapter 7, VXIplug&play for the VXI-MXI-2, or Appendix B, Programmable Configurations, for more information on the MXIbus timer. On a hard reset, these bits are initialized to the value stored in the onboard EEPROM for these bits.
Chapter 5 Register Descriptions DMA Channel Operation Register (CHORx) CHOR1 VXIbus A24 or A32 Offset: D00 (hex) CHOR2 VXIbus A24 or A32 Offset: E00 (hex) Attributes: Read/Write 32, 16, 8-bit accessible 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 CLRDONE 0 0 FRESET ABORT STOP 0 START This register is used to control overall operation of the DMA co
Chapter 5 Register Descriptions 4 FRESET DMA FIFO Reset This bit can be written with a 1 to reset the DMA FIFO. It is necessary to reset the FIFO after an ABORT operation or if a DMA transfer ends due to an error condition. It is not necessary to clear the FRESET bit after writing a 1 to it. The FIFO is reset by a hard reset and is not affected by a soft reset. 3 ABORT Abort DMA Operation This bit can be written with a 1 to abort the current DMA operation.
Chapter 5 0 START Register Descriptions Start DMA Operation This bit should be written with a 1 to start a new DMA operation after the other DMA registers are initialized. This bit can also be set after a DMA operation has been stopped with the STOP bit to allow the operation to complete. When restarting a stopped DMA operation, the START bit should not be set until the DONE bit becomes 1 after setting the STOP bit.
Chapter 5 Register Descriptions DMA Channel Control Register (CHCRx) CHCR1 VXIbus A24 or A32 Offset: D04 (hex) CHCR2 VXIbus A24 or A32 Offset: E04 (hex) Attributes: Read/Write 32, 16, 8-bit accessible 31 30 29 28 27 26 25 24 SET DMAIE CLR DMAIE 0 0 0 0 SET DONEIE CLR DONEIE 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 1 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 This register is used to individually enable the two D
Chapter 5 29-26 0 Register Descriptions Reserved These bits are reserved. Write each of these bits with 0 when writing the CHCRx. The value these bits return when read is meaningless. 25 SET DONEIE Set DONE Interrupt Enable Writing a 1 to this bit enables the corresponding DMA controller to interrupt on the DONE condition in the DMA Channel Status Register (CHSRx). Writing a 0 to this bit has no effect.
Chapter 5 Register Descriptions DMA Transfer Count Register (TCRx) TCR1 VXIbus A24 or A32 Offset: D08 (hex) TCR2 VXIbus A24 or A32 Offset: E08 (hex) Attributes: Read/Write 32, 16, 8-bit accessible 31 30 29 28 27 26 25 24 TC[31] TC[30] TC[29] TC[28] TC[27] TC[26] TC[25] TC[24] 23 22 21 20 19 18 17 16 TC[23] TC[22] TC[21] TC[20] TC[19] TC[18] TC[17] TC[16] 15 14 13 12 11 10 9 8 TC[15] TC[14] TC[13] TC[12] TC[11] TC[10] TC[9] TC[8] 7 6 5 4 3 2 1 0 TC
Chapter 5 Register Descriptions which is described in Chapter 7, VXIplug&play for the VXI-MXI-2. By default, the Transfer Limit is set to Unlimited; with this setting, the transfer count must not exceed 32 KB (8000 hex) if the source of the DMA operation will use synchronous MXIbus burst transfers.
Chapter 5 Register Descriptions DMA Source Configuration Register (SCRx) SCR1 VXIbus A24 or A32 Offset: D0C (hex) SCR2 VXIbus A24 or A32 Offset: E0C (hex) Attributes: Read/Write 32, 16, 8-bit accessible 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 1 1 1 0 0 0 0 0 15 14 13 12 11 10 9 8 0 BLOCKEN 0 0 0 ASCEND TSIZE[1] TSIZE[0] 7 6 5 4 3 2 1 0 PORT[1] PORT[0] AM[5] AM[4] AM[3] AM[2] AM[1] AM[0] This register is used to conf
Chapter 5 14 BLOCKEN Register Descriptions Block Mode DMA Write a 1 to this bit to cause the DMA controller to perform block-mode transfers to the source. During block mode, the DMA controller keeps the AS* signal asserted throughout a series of read cycles to the source. The DMA controller automatically deasserts and reasserts the AS* signal when it reaches the appropriate transfer size limit for the bus on which the source is located (for example 256 bytes on the VXIbus).
Chapter 5 Register Descriptions 9-8 TSIZE[1:0] Transfer Size These bits control the transfer size to be used to access the source. Write these bits with 01 (binary) to perform 8-bit transfers, 10 (binary) to perform 16-bit transfers, and 11 (binary) to perform 32-bit or 64-bit transfers. The DMA controller can distinguish between 32-bit and 64-bit transfers using the AM[5:0] bits. These bits are cleared by a hard reset and are not affected by a soft reset.
Chapter 5 Register Descriptions DMA Source Address Register (SARx) SAR1 VXIbus A24 or A32 Offset: D10 (hex) SAR2 VXIbus A24 or A32 Offset: E10 (hex) Attributes: Read/Write 32, 16, 8-bit accessible 31 30 29 28 27 26 25 24 SA[31] SA[30] SA[29] SA[28] SA[27] SA[26] SA[25] SA[24] 23 22 21 20 19 18 17 16 SA[23] SA[22] SA[21] SA[20] SA[19] SA[18] SA[17] SA[16] 15 14 13 12 11 10 9 8 SA[15] SA[14] SA[13] SA[12] SA[11] SA[10] SA[9] SA[8] 7 6 5 4 3 2 1 0 SA
Chapter 5 Register Descriptions source. To compute this value from the VXIbus address of the source, just subtract the VXI-MXI-2 module’s A24 or A32 base address.
Chapter 5 Register Descriptions DMA Destination Configuration Register (DCRx) DCR1 VXIbus A24 or A32 Offset: D14 (hex) DCR2 VXIbus A24 or A32 Offset: E14 (hex) Attributes: Read/Write 32, 16, 8-bit accessible 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 1 1 1 0 0 0 0 0 15 14 13 12 11 10 9 8 0 BLOCKEN 0 0 0 ASCEND TSIZE[1] TSIZE[0] 7 6 5 4 3 2 1 0 PORT[1] PORT[0] AM[5] AM[4] AM[3] AM[2] AM[1] AM[0] This register is used to
Chapter 5 Register Descriptions 14 BLOCKEN Block Mode DMA Write a 1 to this bit to cause the DMA controller to perform block-mode transfers to the destination. During block mode, the DMA controller keeps the AS* signal asserted throughout a series of write cycles to the destination. The DMA controller automatically deasserts and reasserts the AS* signal when it reaches the appropriate transfer size limit for the bus on which the destination is located (for example 256 bytes on the VXIbus).
Chapter 5 9-8 TSIZE[1:0] Register Descriptions Transfer Size These bits control the transfer size to be used to access the destination. Write these bits with 01 (binary) to perform 8-bit transfers, 10 (binary) to perform 16-bit transfers, and 11 (binary) to perform 32-bit or 64-bit transfers. The DMA controller can distinguish between 32-bit and 64-bit transfers using the AM[5:0] bits. These bits are cleared by a hard reset and are not affected by a soft reset.
Chapter 5 Register Descriptions DMA Destination Address Register (DARx) DAR1 VXIbus A24 or A32 Offset: D18 (hex) DAR2 VXIbus A24 or A32 Offset: E18 (hex) Attributes: Read/Write 32, 16, 8-bit accessible 31 30 29 28 27 26 25 24 DA[31] DA[30] DA[29] DA[28] DA[27] DA[26] DA[25] DA[24] 23 22 21 20 19 18 17 16 DA[23] DA[22] DA[21] DA[20] DA[19] DA[18] DA[17] DA[16] 15 14 13 12 11 10 9 8 DA[15] DA[14] DA[13] DA[12] DA[11] DA[10] DA[9] DA[8] 7 6 5 4 3 2 1
Chapter 5 Register Descriptions VXIbus address of the destination. To compute this value from the VXIbus address of the destination, just subtract the VXI-MXI-2 module’s A24 or A32 base address.
Chapter 5 Register Descriptions DMA Channel Status Register (CHSRx) CHSR1 VXIbus A24 or A32 Offset: D3C (hex) CHSR2 VXIbus A24 or A32 Offset: E3C (hex) Attributes: Read Only 32, 16, 8-bit accessible 31 30 29 28 27 26 25 24 INT 0 0 0 0 0 DONE 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ERROR SABORT 0 STOPS 0 0 XFERR 0 7 6 5 4 3 2 1 0 0 0 0 0 SERR[1] SERR[0] DERR[1] DERR[0] This register provides status bits for DMA c
Chapter 5 Register Descriptions (ERROR, SABORT, STOPS, XFERR, SERR[1:0], and DERR[1:0]) should be checked before assuming the transfer completed successfully. 24-16 0 Reserved These bits are reserved. The value these bits return when read is meaningless. 15 ERROR DMA Error bit When this bit returns a 1 it indicates that the corresponding DMA controller terminated an operation due to an error condition. The other bits in this register can be used to determine the type of error.
Chapter 5 Register Descriptions 8-4 0 Reserved These bits are reserved. The value these bits return when read is meaningless. 3-2 SERR[1:0] Source Error Status These bits indicate the type of error that occurred when accessing the source. When 00 (binary) is returned, no error occurred. When 01 (binary) is returned, a data transfer to the source got a bus error. When 10 (binary) is returned, it indicates that the retry limit was exceeded trying to access the source.
Chapter 5 Register Descriptions DMA FIFO Count Register (FCRx) FCR1 VXIbus A24 or A32 Offset: D40 (hex) FCR2 VXIbus A24 or A32 Offset: E40 (hex) Attributes: Read Only 32, 16, 8-bit accessible 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 ECR[7] ECR[6] ECR[5] ECR[4] ECR[3] ECR[2] ECR[1] ECR[0] 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 FCR[7] FCR[6] FCR[5] FCR[4] FCR[3] FCR[2] FCR[1] FCR[0] This register indicat
Chapter System Configuration 6 This chapter explains important considerations for programming and configuring a VXIbus/MXIbus system using VXI-MXI-2 mainframe extenders. Note: Detailed descriptions of all register bits can be found in Chapter 5, Register Descriptions. In a MXIbus system, MXIbus address space is partitioned between MXIbus devices. A MXIbus device is any device having a MXIbus interface. MXIbus devices can be VXIbus mainframes, PCs, or stand-alone instruments.
Chapter 6 System Configuration Planning a VXIbus/MXIbus System Logical Address Map The VXIbus/MXIbus system integrator is the person who configures all the VXIbus and MXIbus devices and connects the system together. This chapter assumes that you are the system integrator. Before you begin setting the logical addresses of the devices in your VXIbus/MXIbus system, you must determine the tree configuration of your system.
VXI-MXI-2 VXI-MXI-2 Chapter 6 VXIbus Mainframe VXIbus Mainframe VXI-MXI-2 VXIbus Mainframe VXI-MXI-2 VXI-MXI-2 VXI-MXI-2 Multiframe Resource Manager Root MXIbus Device VXIbus Mainframe System Configuration MXIbus Device Level 1 Level 2 Figure 6-2. VXIbus/MXIbus System with Multiframe RM in a VXIbus Mainframe The recommended way to set up your system is to fill up Level 1 MXIbus links before adding additional levels.
Chapter 6 System Configuration zeros gives the actual base address of the window. In other words, the Base and Size define a range of addresses that are in the window. A Direction bit is also included to indicate whether the defined range of addresses are mapped into or out of the VXIbus mainframe. Table 6-1 shows which bits are compared for each Size setting and the resulting address range in hex if Base is set to 0 and hex 55.
Chapter 6 F E D C B A 9 8 7 6 5 4 3 2 1 System Configuration 0 FF-F0 EF-E0 DF-D0 CF-C0 Size = 1 BF-B0 AF-A0 9F-90 8F-80 Size = 0 7F-70 6F-60 Size = 2 5F-50 4F-40 3F-30 Size = 3 2F-20 Size = 4 1F-10 0F-00 Size = 5 Size = 6 Size = 7 Figure 6-4.
Chapter 6 System Configuration Steps to Follow When Planning a System Logical Address Map As system integrator, when installing devices in the VXIbus/MXIbus system, you must assign a range of logical addresses for each VXIbus mainframe and MXIbus link.
VXI-MXI-2 VXI-MXI-2 Chapter 6 Multiframe Resource Manager System Configuration VXIbus Mainframe #1 MXIbus #1 MXIbus #2 VXI-MXI-2 VXIbus Mainframe #2 VXI-MXI-2 MXIbus Device B VXI-MXI-2 MXIbus Device A VXI-MXI-2 Level 1 VXIbus Mainframe #3 VXIbus Mainframe #6 MXIbus #3 VXI-MXI-2 VXI-MXI-2 Level 2 VXIbus Mainframe #4 VXIbus Mainframe #5 Figure 6-5. Example VXIbus/MXIbus System Table 6-2.
Chapter 6 System Configuration 2. Note: Determine the number of logical addresses required by the root device. If the RM is a PC with a MXIbus interface, the total number of logical addresses required is 1. If the RM is in a VXIbus mainframe, determine the number of logical addresses required by all devices in that mainframe. Fill in that number in the appropriate space in the RM block as shown in Figure 6-7.
Chapter 6 System Configuration For the example system, MXIbus #3 is a second-level MXIbus link and it is connected to VXIbus Mainframe #3. We filled out the worksheet in Figure 6-10 for MXIbus #3 and entered the results into the worksheet for MXIbus #1 (Figure 6-8) under the device VXIbus Mainframe #3. MXIbus #3 needs 32 logical addresses and the devices in VXIbus Mainframe #3 need eight logical addresses. The sum of these numbers is 40, which rounds up to 64. 5.
Chapter 6 System Configuration Device B F E D C B A 9 8 7 6 5 4 3 2 1 0 FF-F0 Device A EF-E0 DF-D0 VXIbus Mainframe #2 CF-C0 MXIbus #1 BF-B0 VXIbus Mainframe #5 AF-A0 VXIbus Mainframe #4 MXIbus #3 Into VXIbus Mainframe #3 9F-90 8F-80 VXIbus Mainframe #3 7F-70 6F-60 5F-50 4F-40 3F-30 2F-20 1F-10 0F-00 VXIbus Mainframe #6 MXIbus #2 VXIbus Mainframe #1 Figure 6-6.
Chapter 6 9. System Configuration Determine the range of addresses that will be occupied by each device in the first-level MXIbus links. Remember that the range of addresses occupied by these devices must be within the range of addresses assigned to MXIbus link to which it is a member. Start with the largest device in the MXIbus link. In the example system, MXIbus #1 has four devices. The largest one is VXIbus Mainframe #3, which requires 64 logical addresses.
Chapter 6 System Configuration Resource Manager Mainframe: VXIbus Mainframe #1 Total number of logical addresses required by this device: Round total number up to the next power of two: First-Level MXIbus Link: MXIbus #1 (Fill in after completing charts on the following pages) Total number of logical addresses required by MXIbus Link: Round total number up to next power of two: * 12 16 (24) Range = Size = 0–F 8-4 = 4 Range = Size = 80 – FF 8-7 = 1 Range = Size = 10 – 17 8-3 = 5 * 101 128 (27) F
Chapter 6 MXIbus Link: System Configuration MXIbus #1 Device: MXIbus Device A Number of logical addresses required by device: Round total number up to the next power of two: List other MXIbus links to this mainframe: Number of logical addresses required by additional MXIbus links: Total number of logical addresses required by this device: Round total number up to the next power of two: Device: MXIbus Device B Number of logical addresses required by device: Round total number up to the next power of two:
Chapter 6 System Configuration MXIbus Link: MXIbus #2 Device: VXIbus Mainframe #6 Number of logical addresses required by device: Round total number up to the next power of two: List other MXIbus links to this mainframe: Number of logical addresses required by additional MXIbus links: Total number of logical addresses required by this device: Round total number up to the next power of two: Device: Number of logical addresses required by device: Round total number up to the next power of two: List other MX
Chapter 6 System Configuration Worksheets for Planning Your VXIbus/MXIbus Logical Address Map Use the worksheets on the following pages for analyzing your own VXIbus/MXIbus system. Follow the procedures used to fill out the worksheets for the example VXIbus/MXIbus system. F E D C B A 9 8 7 6 5 4 3 2 1 0 FF-F0 EF-E0 DF-D0 CF-C0 BF-B0 AF-A0 9F-90 8F-80 7F-70 6F-60 5F-50 4F-40 3F-30 2F-20 1F-10 0F-00 Figure 6-11.
Chapter 6 System Configuration Resource Manager Mainframe: Total number of logical addresses required by this device: Round total number up to the next power of two: First-Level MXIbus Link: (Fill in after completing charts on the following pages) Total number of logical addresses required by MXIbus Link: Round total number up to next power of two: * Range = Size = * Range = Size = First-Level MXIbus Link: (Fill in after completing charts on the following pages) Total number of logical addresses requ
Chapter 6 MXIbus Link: System Configuration MXIbus #1 Device: Number of logical addresses required by device: Round total number up to the next power of two: List other MXIbus links to this mainframe: Number of logical addresses required by additional MXIbus links: Total number of logical addresses required by this device: Round total number up to the next power of two: Device: Number of logical addresses required by device: Round total number up to the next power of two: List other MXIbus links to this
Chapter 6 System Configuration MXIbus Link: MXIbus #2 Device: Number of logical addresses required by device: Round total number up to the next power of two: List other MXIbus links to this mainframe: Number of logical addresses required by additional MXIbus links: Total number of logical addresses required by this device: Round total number up to the next power of two: Device: Number of logical addresses required by device: Round total number up to the next power of two: List other MXIbus links to this
Chapter 6 MXIbus Link: System Configuration MXIbus #3 Device: Number of logical addresses required by device: Round total number up to the next power of two: List other MXIbus links to this mainframe: Number of logical addresses required by additional MXIbus links: Total number of logical addresses required by this device: Round total number up to the next power of two: Device: Number of logical addresses required by device: Round total number up to the next power of two: List other MXIbus links to this
Chapter 6 System Configuration Alternative Worksheets for Planning Your VXIbus/MXIbus Logical Address Map For most VXIbus/MXIbus systems, you may find the following worksheet helpful when setting up a system using the High/Low format for window configuration. The entire system can be described on one worksheet. Remember that the High/Low format cannot be used with a standard VXIbus Resource Manager.
Chapter 6 System Configuration Device VXI #1 Device LAs 12 Range IN 0 – 11 Lower LAs Range OUT Lower LAs Range OUT Lower LAs Range OUT Lower LAs Range OUT Lower LAs Range OUT Lower LAs Range OUT MXI#1 Device MXI A Device MXI B VXI #2 Device Device VXI #3 Device Device LAs 3 Device LAs 1 Device LAs 23 Device LAs 6 Device LAs Lower LAs 0 Lower LAs 0 Lower LAs 0 Lower LAs 22 Lower LAs Total LAs 3 Total LAs 1 Total LAs 23 Total LAs 28 Total LAs Range IN 12–14 Range
Chapter 6 System Configuration Device Device LAs Range IN Lower LAs Range OUT Lower LAs Range OUT Lower LAs Range OUT Lower LAs Range OUT Lower LAs Range OUT Lower LAs Range OUT MXI#1 Device Device Device Device Device Device LAs Device LAs Device LAs Device LAs Device LAs Lower LAs Lower LAs Lower LAs Lower LAs Lower LAs Total LAs Total LAs Total LAs Total LAs Total LAs Range IN Range IN Range IN Range IN Range IN Range OUT Range OUT Range OUT Range OUT Range OUT Devic
Chapter 6 System Configuration Planning a VXIbus/MXIbus System A16 Address Map The VXIbus specification does not define a method for dynamically determining the amount of A16 space each device requires. The specification defines the upper 16 KB of A16 space for VXIbus device configuration registers. In most cases, the lower 48 KB of A16 space are used for VMEbus devices installed in the VXIbus system. In a VXIbus/MXIbus system, A16 space is defined as that lower 48 KB of the A16 address space.
Chapter 6 System Configuration F00 E00 D00 C00 B00 A00 900 800 700 600 500 400 300 200 100 000 BFFF-B000 Size = 5 Size = 7 Size = 6 Size = 4 AFFF-A000 9FFF-9000 Size = 3 8FFF-8000 7FFF-7000 6FFF-6000 Size = 0 Size = 2 5FFF-5000 4FFF-4000 Size = 1 3FFF-3000 2FFF-2000 1FFF-1000 0FFF-0000 Figure 6-18. A16 Space Allocations for all Size Values To plan the A16 address map, you will follow procedures similar to those for planning the logical address space address map.
Chapter 6 System Configuration devices. VXIbus Mainframe #3 needs 4 KB of A16, in addition to the amount of A16 required by MXIbus link #3 connected to it on Level 2. 4. Figure 6-23 is the worksheet for MXIbus #3, which includes VXIbus Mainframes #4 and #5. Mainframe #4 needs 2 KB and Mainframe #5 needs 1 KB of A16 space. We fill in the appropriate spaces on the worksheet. 5.
Chapter 6 System Configuration 10. Each first-level MXIbus link is connected to the RM through a VXI-MXI-2. The A16 window for MXIbus link #1 is 16 KB in size. We assign the next lowest available 16 KB portion of A16 space to MXIbus link #1, which is address range 4000 to 7FFF hex. (See Figure 6-20.) The base address of this window is 4000, which we enter into Figure 6-21. The Size field for the window is i where the size of the window = 256 * 2 8-i. 16 KB = 256 * 2 8-2, so Size = 2.
VXI-MXI-2 VXI-MXI-2 Chapter 6 Multiframe Resource Manager System Configuration VXIbus Mainframe #1 MXIbus #1 MXIbus #2 VXI-MXI-2 VXIbus Mainframe #2 VXI-MXI-2 MXIbus Device B VXI-MXI-2 MXIbus Device A VXI-MXI-2 Level 1 VXIbus Mainframe #3 VXIbus Mainframe #6 MXIbus #3 VXI-MXI-2 VXI-MXI-2 Level 2 VXIbus Mainframe #4 VXIbus Mainframe #5 Figure 6-19. Example VXIbus/MXIbus System Diagram Table 6-4.
Chapter 6 System Configuration F00 E00 D00 C00 B00 A00 900 800 700 600 500 400 300 200 100 000 BFFF-B000 AFFF-A000 9FFF-9000 VXIbus Mainframe #6 8FFF-8000 7FFF-7000 MXIbus Device A 6FFF-6000 MXIbus #1 VXIbus Mainframe #4 5FFF-5000 4FFF-4000 VXIbus Mainframe #5 VXIbus Mainframe #3 3FFF-3000 2FFF-2000 VXIbus Mainframe #1 1FFF-1000 0FFF-0000 Figure 6-20.
Chapter 6 Resource Manager Mainframe: VXIbus Mainframe #1 Amount of A16 space required for this mainframe: Round up to next address break: First-Level MXIbus Link: MXIbus #1 Amount of A16 space required for devices connected to this VXI-MXI-2: Round up to next address break: A16 Window: Base 4000 Size: 2 Direction: First-Level MXIbus Link: MXIbus #2 Amount of A16 space required for devices connected to this VXI-MXI-2: Round up to next address break: A16 Window: Base 8000 Size: 5 Direction: First-Level MXIb
Chapter 6 System Configuration MXIbus Link: MXIbus #1 Device: MXIbus Device A Amount of A16 space required by this device: A16 space requirement for each second-level MXIbus link connected to this device: #1 + #2 Round up to next address break: Total amount of A16 space required for this window: Round up total amount to the next address size break: First-Level VXI-MXI-2: A16 Window: Base: Size: Direction: Second-Level VXI-MXI-2 #1: A16 Window: Base: Size: Direction: Second-Level VXI-MXI-2 #2: A16 Window:
Chapter 6 System Configuration MXIbus Link: MXIbus #1 (Continued) Device: VXIbus Mainframe #3 Amount of A16 space required by this device: A16 space requirement for each second-level MXIbus link connected to this device: #1 2 KB + 1 KB + #2 Round up to next address break: 4 KB Total amount of A16 space required for this window: Round up total amount to the next address size break: First-Level VXI-MXI-2: A16 Window: Base: 4000 Size: 3 Direction: In Second-Level VXI-MXI-2 #1: MXIbus #3 A16 Window: Base: 500
Chapter 6 System Configuration MXIbus Link: MXIbus #3 Device: VXIbus Mainframe #4 Amount of A16 space required by this device: A16 space requirement for each second-level MXIbus link connected to this device: #1 + #2 Round up to next address break: Total amount of A16 space required for this window: Round up total amount to the next address size break: First-Level VXI-MXI-2: A16 Window: Base: 5000 Size: 5 Direction: In Second-Level VXI-MXI-2 #1: A16 Window: Base: Size: Direction: Second-Level VXI-MXI-2 #2
Chapter 6 System Configuration Worksheets for Planning Your VXIbus/MXIbus A16 Address Map Use the worksheets on the following pages for planning an A16 address map for your VXIbus/ MXIbus system. Follow the procedures used to fill out the worksheets for the sample VXIbus/ MXIbus system. F00 E00 D00 C00 B00 A00 900 800 700 600 500 400 300 200 100 000 BFFF-B000 AFFF-A000 9FFF-9000 8FFF-8000 7FFF-7000 6FFF-6000 5FFF-5000 4FFF-4000 3FFF-3000 2FFF-2000 1FFF-1000 0FFF-0000 Figure 6-24.
Chapter 6 System Configuration Resource Manager Mainframe: Amount of A16 space required for this mainframe: Round up to next address break: * First-Level MXIbus Link: Amount of A16 space required for devices connected to this VXI-MXI-2: Round up to next address break: A16 Window: Base Size: Direction: First-Level MXIbus Link: Amount of A16 space required for devices connected to this VXI-MXI-2: Round up to next address break: A16 Window: Base Size: Direction: First-Level MXIbus Link: Amount of A16 space
Chapter 6 MXIbus Link: System Configuration MXIbus #1 Device: Amount of A16 space required by this device: A16 space requirement for each second-level MXIbus link connected to this device: #1 + #2 Round up to next address break: Total amount of A16 space required for this window: Round up total amount to the next address size break: First-Level VXI-MXI-2: A16 Window: Base: Size: Direction: Second-Level VXI-MXI-2 #1: A16 Window: Base: Size: Direction: Second-Level VXI-MXI-2 #2: A16 Window: Base: Size: Di
Chapter 6 System Configuration MXIbus Link: MXIbus #2 Device: Amount of A16 space required by this device: A16 space requirement for each second-level MXIbus link connected to this device: #1 + #2 Round up to next address break: Total amount of A16 space required for this window: Round up total amount to the next address size break: First-Level VXI-MXI-2: A16 Window: Base: Size: Direction: Second-Level VXI-MXI-2 #1: A16 Window: Base: Size: Direction: Second-Level VXI-MXI-2 #2: A16 Window: Base: Size: Di
Chapter 6 MXIbus Link: System Configuration MXIbus #3 Device: Amount of A16 space required by this device: A16 space requirement for each second-level MXIbus link connected to this device: #1 + #2 Round up to next address break: Total amount of A16 space required for this window: Round up total amount to the next address size break: First-Level VXI-MXI-2: A16 Window: Base: Size: Direction: Second-Level VXI-MXI-2 #1: A16 Window: Base: Size: Direction: Second-Level VXI-MXI-2 #2: A16 Window: Base: Size: Di
Chapter 6 System Configuration MXIbus Link: MXIbus #4 Device: Amount of A16 space required by this device: A16 space requirement for each second-level MXIbus link connected to this device: #1 + #2 Round up to next address break: Total amount of A16 space required for this window: Round up total amount to the next address size break: First-Level VXI-MXI-2: A16 Window: Base: Size: Direction: Second-Level VXI-MXI-2 #1: A16 Window: Base: Size: Direction: Second-Level VXI-MXI-2 #2: A16 Window: Base: Size: Di
Chapter 6 System Configuration Multiframe RM Operation On power-up, all MXIbus devices are isolated from each other because all address mapping windows are disabled.
Chapter 6 System Configuration Notice that it is not possible to detect duplicate logical addresses because devices are found by reading the VXIbus ID Register. If two devices share a logical address, they will both respond to an address access without any indication of an error. B. For each VXI-MXI-2 found in the mainframe, starting with the lowest addressed VXI-MXI-2, the RM: i. Sets the VXI-MXI-2 logical address window to map all of the logical address space outward and enables the window. ii.
Chapter 6 System Configuration Table 6-5.
Chapter 6 System Configuration VXI-MXI-2 User Manual 4. Enables the logical address window of the VXI-MXI-2 found at logical address 82 for the entire outward mapping range of 0 to FF. Scans all logical addresses, skipping all previously encountered devices, and finds the VXI-MXI-2 in VXIbus Mainframe #4 and the VXI-MXI-2 in VXIbus Mainframe #5. 5. Enables the logical address window of the VXI-MXI-2 in VXIbus Mainframe #4 for the entire inward mapping range of 0 to FF.
Chapter 6 9. System Configuration Enables the logical address window of the VXI-MXI-2 in VXIbus Mainframe #2 for the entire inward mapping range of 0 to FF. Scans all logical addresses, skipping all previously encountered devices and defined ranges. Finds the Slot 0 device and uses it to move all DC devices in VXIbus Mainframe #2 to the lowest unused logical addresses. No more VXI-MXI-2 interfaces are found.
Chapter 6 System Configuration Configuring the A24 and A32 Addressing Windows After the logical address space is configured for the system, the multiframe RM configures the A16, A24, and A32 address space. The logical address configuration forms a tree topology. Starting at the bottom of the tree and working up, add up the amount of memory needed by each mainframe and the devices on levels below it. That amount is then rounded up to the next power of two if the Base/Size format is used.
Chapter VXIplug&play for the VXI-MXI-2 7 This chapter describes the contents of the VXIplug&play disk that came with your VXI-MXI-2 kit. The disk contains a VXIplug&play soft front panel and a VXIplug&play knowledge base file. VXI-MXI-2 VXIplug&play Soft Front Panel The VXIplug&play soft front panel that comes with your VXI-MXI-2 kit complies with VXIplug&play document VPP-7, Soft Front Panel Specification. This section describes the options you can configure using the soft front panel.
Chapter 7 VXIplug&play for the VXI-MXI-2 where x is the letter of the floppy drive into which you inserted the VXIplug&play disk. Using the Soft Front Panel After successfully running the soft front panel, you will see the panel as shown in Figure 7-1. By default, the opening panel displays the board settings view. Figure 7-1.
Chapter 7 VXIplug&play for the VXI-MXI-2 Click on the OK button to exit the soft front panel and save to the instrument’s onboard EEPROM any changes you have made. Alternatively, you can use the Apply button to save your changes to the EEPROM without exiting the soft front panel, or the Cancel button will exit the panel without saving any changes.
Chapter 7 VXIplug&play for the VXI-MXI-2 These controls are necessary if you change the amount of DRAM installed on the VXI-MXI-2. The amount of memory you set with the Requested Memory control should match the amount of DRAM installed on the VXI-MXI-2. If no DRAM is installed, you should set it to 16 KB. Notice that the smallest valid amount in A32 space is 64 KB. Caution: If you install DRAM into the VXI-MXI-2, do not attempt to use the first 4 KB of memory space.
Chapter 7 VXIplug&play for the VXI-MXI-2 Interlocked Interlocked arbitration mode is an optional mode of operation in which at any given moment the system can perform as if it were one large VXIbus mainframe with only one master of the entire system—VXIbus and MXIbus. This mode of operation prevents deadlocks by interlocking all arbitration in the VXIbus/MXIbus system. The options for this control are Enabled and Disabled.
Chapter 7 VXIplug&play for the VXI-MXI-2 This type of system configuration is recommended if you have one of the following situations: • A VXIbus mainframe with only slave devices and no masters. Without bus masters, there is no chance for deadlock. You can configure the VXI-MXI-2 devices in this mainframe for normal operating mode. • A VXIbus mainframe with both masters and slaves, but the masters communicate only with the slaves in their mainframe.
Chapter 7 VXIplug&play for the VXI-MXI-2 VXI Bus Settings Use the options in this group to control features of the VXIbus interface on the VXI-MXI-2. Access these controls by setting the View control to VXIbus as shown in Figure 7-2. Figure 7-2. VXI-MXI-2 VXIplug&play Soft Front Panel VXIbus Settings System Controller You can use the System Controller control to override the jumper setting on the VXI-MXI-2.
Chapter 7 VXIplug&play for the VXI-MXI-2 Warning: Do not install a VXI-MXI-2 configured for VMEbus System Controller (VXI Slot 0) into another slot without first reconfiguring it to either Non-Slot 0 or automatic configuration. Neglecting to do this could result in damage to the VXI-MXI-2, the VXIbus backplane, or both.
Chapter 7 VXIplug&play for the VXI-MXI-2 Arbiter Timeout An arbitration timeout feature is available on the VXI-MXI-2 when it is acting as the VMEbus arbiter. This feature applies only to a VXIbus Slot 0 VXI-MXI-2. The default value is Enabled. The timer begins when the arbiter circuit on the VXI-MXI-2 drives one of the BGOUT lines on the backplane. If no device takes over the bus within the timeout limit, the BGOUT is removed and the bus is either idle or granted to another requester.
Chapter 7 VXIplug&play for the VXI-MXI-2 Auto Retry The VXI-MXI-2 has an automatic retry feature for cycles that map from the VXIbus to the MXIbus. You can select Enabled or Disabled for this control. By default this option is disabled. Normally, when a cycle maps from the VXIbus to the MXIbus, any retry response received on the MXIbus is passed to the VXIbus.
Chapter 7 VXIplug&play for the VXI-MXI-2 System Controller You can use the System Controller control to determine whether the VXI-MXI-2 acts as the MXIbus System Controller. When the Auto setting (the default setting) is active, the VXI-MXI-2 automatically can sense from the MXIbus cable whether it should be the controller. You can select either Yes or No to manually determine if the VXI-MXI-2 should be the MXIbus System Controller.
Chapter 7 VXIplug&play for the VXI-MXI-2 Auto Retry The VXI-MXI-2 has an automatic retry feature for cycles that map from the MXIbus to the VXIbus. This feature works in the same manner as the Auto Retry control described previously under the VXI Bus Settings section. You can select Enabled or Disabled for this control. By default, this option is disabled. Normally, when a cycle maps from the MXIbus to the VXIbus, any retry response received on the VXIbus is passed to the MXIbus.
Chapter 7 VXIplug&play for the VXI-MXI-2 CLK10 The VXI-MXI-2 can either receive or drive the MXIbus CLK10 signal. In the default setting of Switch, the C-size VXI-MXI-2 uses the switch setting of S7 for this determination; use switch S1 if you have a VXI-MXI-2/B. You can use the Drive or Receive options of the CLK10 feature to override the switch setting and control the direction of the MXIbus CLK10 signal.
Appendix A Specifications This appendix lists various module specifications of the VXI-MXI-2, such as physical dimensions and power requirements. These specifications apply equally to the VXI-MXI-2/B unless otherwise noted.
Appendix A Specifications VMEbus Capability Codes Capability Code Description A32, A24, A16 (master) VMEbus master A32, A24, and A16 addressing A32, A24, A16 (slave) VMEbus slave A32, A24, and A16 addressing D32, D16, D08(EO) (master) VMEbus master D32, D16, and D08 data sizes D32, D16, D08(EO) (slave) VMEbus slave D32, D16, and D08 data sizes BLT, MBLT (master) VMEbus master block and D64 transfers BLT, MBLT (slave) VMEbus slave block and D64 transfers RMW (master) VMEbus master read/modif
Appendix A Specifications Environmental C-Size VXI-MXI-2 Characteristic Specification Temperature 0° to 55° C operating; -40° to 85° C storage Relative Humidity 0% to 95% noncondensing, operating; 0% to 95% noncondensing, storage EMI FCC Class A Verified Random Vibration Operational: 5 to 500 Hz, 0.3 g, 3 axes Non-operational: 5 to 500 Hz, 2.41 g, 3 axes Functional Shock (see Note below) MIL-T-28800E Class 3 (per Section 4.5.5.4.
Appendix A Specifications Requirements Characteristic Specification VXIbus Configuration Space 64 B A24 or A32 Space 16 KB minimum (programmable) Physical C-Size VXI-MXI-2 Characteristic Specification Board Dimensions Fully enclosed, shielded VXI C-size board 233.35 by 340 mm (9.187 by 13.386 in.
Appendix A Specifications Electrical DC Current Ratings Source Typical Maximum 2.5 A 3.5 A -5.
Appendix B Programmable Configurations This appendix describes some features of the VXI-MXI-2 that are configured by programming an onboard EEPROM through software rather than by onboard switches or jumpers. Configuring the EEPROM The EEPROM settings are loaded into the VXI-MXI-2 registers after each power-up or hard reset. The VXI-MXI-2 must be reset either with a power cycle or by asserting the VMEbus SYSRESET * signal after the EEPROM is written for the changes to take effect.
Appendix B Programmable Configurations After all changes have been written to the EEPROM, the 32-bit value stored at offset 2FFC hex from the VXI-MXI-2 A24 or A32 base address should be incremented. This 32-bit value stores the number of times the EEPROM has been written, since there is a limit of 10,000 writes before writes to the part become unreliable. The 32-bit value can be read with a 32-bit access but must be written with 8-bit accesses followed by reads as described in the previous paragraph.
Appendix B Programmable Configurations a24_byte_write(202FFF, writecount & 000000FF); do { a24_byte_read(202FFF, temp); } while (temp != writecount & 000000FF); } else { /* write limit reached */ print("Write limit reached - can't write."); } a24_byte_write(20075B, 01); /* clear IOCONFIG in VMCR2 */ The following sections describe the features that you can configure by writing to the EEPROM on the VXI-MXI-2.
Appendix B Programmable Configurations To change the amount of space that the VXI-MXI-2 requests, write the EEPROM byte at offset 201E hex from the VXI-MXI-2 base address. The following table gives the value that should be written for the corresponding size. Notice that the value you should write for any given size differs depending on whether you are requesting A24 or A32 space.
Appendix B Programmable Configurations VMEbus Timer Limit The VMEbus Bus Timeout (BTO) is a watchdog timer for transfers on the VMEbus Data Transfer bus. After the specified amount of time has elapsed, the BTO circuitry terminates a VMEbus cycle if no slave has responded. The VXI-MXI-2 must provide the VMEbus BTO for proper operation because when a MXIbus cycle is involved, the VMEbus timeout must be disabled and the MXIbus BTO enabled.
Appendix B Programmable Configurations VMEbus Arbiter Arbiter Type You can configure the VXI-MXI-2 as either a Priority or Round Robin VMEbus arbiter. This setting is applicable only if the VXI-MXI-2 you are configuring is the first slot device. The default is Priority. When configured for Priority arbitration, the VXI-MXI-2 grants the bus to the highest bus request level pending.
Appendix B Programmable Configurations VMEbus Requester Request Level The VXI-MXI-2 uses one of the four VMEbus request levels (0 to 3) to request use of the VME Data Transfer Bus (DTB). The VXI-MXI-2 requests use of the DTB whenever an external MXIbus device attempts a transfer that maps into the VXIbus mainframe. The VXI-MXI-2 uses VMEbus request level 3 in its factory-default setting, as required by the VXIbus specification. This is suitable for most VXIbus systems.
Appendix B Programmable Configurations MXIbus Timer Limit The MXIbus Bus Timeout (BTO) is a watchdog timer for transfers on the MXIbus. The MXIbus BTO unit operates only when the VXI-MXI-2 is acting as the MXIbus System Controller. The functionality is similar to that of the VMEbus timer limit described previously. The options range from 8 µs to 128 ms, with a default value of 1 ms. After the specified amount of time has elapsed, the BTO circuitry terminates a MXIbus cycle if no slave has responded.
Appendix B Programmable Configurations MXIbus Fair Requester and MXIbus Parity Checking You can configure whether the VXI-MXI-2 acts as either a fair or unfair requester on the MXIbus. The default is a fair requester, which causes the VXI-MXI-2 to request the MXIbus only when there are no requests pending from other masters. This prevents other masters from being starved of bandwidth. The VXI-MXI-2 will request the bus at any time when configured for unfair operation.
Appendix VXI-MXI-2 Front Panel Configuration C This appendix describes the front panel and connectors on the VXI-MXI-2 interface module. This material contains the information relevant to VXIplug&play Specification VPP-8, VXI Module/ Mainframe to Receiver Interconnection. The VXI-MXI-2 module is National Instruments part number 183345x-01 and the VXI-MXI-2/B is part number 183105x-11, where x is the hardware revision letter.
Appendix C VXI-MXI-2 Front Panel Configuration mm (inches) 12.7 (.5) SYSFAIL MXI VXI 70.13 (2.76) MXIbus 197.13 207.29 217.45 (7.76) (8.16) (8.56) 15.11 (.595) 12.95 (.51) EXT CLK TRG OUT TRG IN RESET Intermodule Separation Plane Figure C-1.
Appendix C mm (inches) VXI-MXI-2 Front Panel Configuration 4.83 (.190) 2.67 (.105) SYSFAIL MXI VXI 70.13 (2.76) MXIbus 197.13 207.29 217.45 (7.761) (8.161) (8.561) TRG IN TRG OUT EXT CLK RESET Figure C-2.
Appendix C VXI-MXI-2 Front Panel Configuration Front Panel Connectors The front panel has a MXI-2 connector that connects the VXI-MXI-2 to the MXIbus, and three type SMB connectors for connection to the external clock, trigger output, and trigger input. MXI-2 Connector The MXI-2 connector is a 144-pin female connector manufactured by Meritec (Meritec part number 182800A-01). The mating cable assembly is National Instruments part number 182801A-xxx, where xxx is the length in meters.
Appendix C VXI-MXI-2 Front Panel Configuration Table C-1.
Appendix C VXI-MXI-2 Front Panel Configuration The characteristic impedance of the MXIbus signals is 120 Ω. Table C-2 lists additional characteristics of the MXIbus signals. Table C-2. MXIbus Signal Characteristics Signal Category Voltage Range Max Current Frequency Range Each single-ended signal 0 to 3.4 V 60 mA DC to 10 Mhz Each differential signal (D17–D34) 0 to 5 V 80 mA DC to 10 Mhz Each 5 V (A35, A36) 5V 1.75 A fused DC Each TERMPOWER (B35, B36) 3.4 V 1.
Appendix C VXI-MXI-2 Front Panel Configuration Table C-3 lists characteristics of the EXT CLK connector. Table C-3. EXT CLK Signal Characteristics Impedance Voltage Range Max Current Frequency Range 50 Ω 0 to 5 V 100 mA 10 Mhz Trigger Output Connector The trigger output (TRG OUT) connector is a male SMB connector manufactured by Applied Engineering Products, part number 2110-1511-000. The mating connector is Applied Engineering Products part number 2002-1551-003.
Appendix C VXI-MXI-2 Front Panel Configuration Trigger Input Connector The trigger input (TRG IN) connector is a male SMB connector manufactured by Applied Engineering Products, part number 2110-1511-000. The mating connector is Applied Engineering Products part number 2002-1551-003. Figure C-6 shows the TRG IN connector on the VXI-MXI-2. Trigger Input Chassis Ground TRG IN Figure C-6. TRG IN Connector Table C-5 lists characteristics of the TRG IN connector. Table C-5.
Differences and Incompatibilities between the VXI-MXI and the VXI-MXI-2 Appendix D This appendix describes the differences and incompatibilities between the first-generation MXIbus-to-VXIbus interface, the VXI-MXI, and the VXI-MXI-2. This information may be helpful for users of the VXI-MXI who are moving to the VXI-MXI-2. MXIbus Connector The VXI-MXI-2 interfaces the VXIbus to the National Instruments next-generation MXIbus (MXI-2), while the VXI-MXI used the firstgeneration MXIbus.
Appendix D Differences and Incompatibilities between the VXI-MXI and the VXI-MXI-2 In addition to the INTX functionality, MXI-2 incorporates new data transfer protocols that achieve higher performance than is possible on the first-generation MXIbus.
Appendix D Differences and Incompatibilities between the VXI-MXI and the VXI-MXI-2 Configurable Feature VXI-MXI-2 Implementation MXIbus Timeout Length Shared MXIbus Status/Control Register (SMSR/SMCR) or EEPROM Shared MXIbus Status/Control Register (SMSR/SMCR) or EEPROM Shared MXIbus Status/Control Register (SMSR/SMCR) or EEPROM MXIbus Fair Requester MXIbus Parity Checking VXIbus Model Code The VXIbus Device Type Register (VDTR) on the VXI-MXI-2 returns a different model code than the VXI-MXI because
Appendix D Differences and Incompatibilities between the VXI-MXI and the VXI-MXI-2 The Backoff Condition Clear bit (BOFFCLR) is no longer implemented. It is not necessary because the BKOFF bit in the VXIbus Interrupt Status Register (VISTR) now clears automatically when read. The MXTRIGINT, MXSRSTINT, MXACFAILINT, and MXSYSFINT bits are no longer implemented in the VXI-MXI-2 Status Register (VMSR).
Appendix D Differences and Incompatibilities between the VXI-MXI and the VXI-MXI-2 (VISTR/VICTR) in Chapter 5 for more information on these alternatives to the local interrupt conditions on the single MXIbus interrupt line. Notice that these same registers and solutions work on an Enhanced VXI-MXI when the destination has an INTX connection.
Appendix Configuring a Two-Frame System E This appendix describes how to configure a system containing two mainframes linked by VXI-MXI-2 mainframe extenders. Configuring Two VXI-MXI-2 Modules for a Two-Frame System The factory configuration of the VXI-MXI-2 is suitable for the most common system configurations. However, if you are setting up a VXI system using VXI-MXI-2 modules to extend from one mainframe to another, you need to reconfigure the VXI-MXI-2 interfaces.
Appendix E Configuring a Two-Frame System Frame A Frame B NATIONAL INSTRUMENTS® bus bus NATIONAL INSTRUMENTS ® Slot 0 Device VXI-MXI-2, non-Slot 0 VXI-MXI-2, Slot 0 Figure E-1. A Two-Frame VXI System In the example shown in Figure E-1, Frame A contains a VXI-MXI-2 configured as a non-Slot 0 device. It is logical address 1 and maps CLK10 from the VXIbus to the MXIbus. Frame B contains a Slot 0 VXI-MXI-2. It is logical address 80 (hex) and maps CLK10 from the MXIbus to the VXIbus.
© National Instruments Corporation E-3 VXI-MXI-2 User Manual Figure E-2.
Appendix E Configuring a Two-Frame System 1 2 3 1 W1 2 S1 3 U20 Figure E-3.
Appendix E Configuring a Two-Frame System VXIbus Logical Address Frame A contains logical addresses in the range of 0 to 7F hex. The Resource Manager must be logical address 0. The VXI-MXI-2 has logical address 1, which is the default logical address. Figure E-4a shows the switch setting for logical address 1 on a C-size VXI-MXI-2. See Figure E-5a if you have a VXI-MXI-2/B. Ensure that no other devices in that frame have either of these logical addresses.
Appendix E Configuring a Two-Frame System Figure E-5 shows switch settings for logical address hex 1 and 80 on a VXI-MXI-2/B. 2 3 4 5 6 7 8 U20 1 a. Switch Set to Logical Address 1 (Default) 2 3 4 5 6 7 8 U20 1 b. Switch Set to Logical Address Hex 80 Figure E-5. Logical Address Selection on a VXI-MXI-2/B VXIbus CLK10 Routing for a Two-Frame System The VXI-MXI-2 in Frame A routes CLK10 from the VXIbus to the MXIbus.
Appendix E Configuring a Two-Frame System To configure the Frame A VXI-MXI-2 to drive the MXIbus CLK10, change the setting of S7 as shown in Figure E-6b if you have a C-size VXI-MXI-2, or change the setting of S1 as shown in Figure E-7b if you have a VXI-MXI-2/B. The setting of the W3 jumper (W1 on a VXI-MXI-2/B) does not matter because the VXI-MXI-2 is not in Slot 0 and will not be driving the VXIbus CLK10.
Appendix E Configuring a Two-Frame System From onboard oscillator W3 From SMB (S3 must be set to "IN") Receive CLK10 from MXIbus From MXIbus S7 OUT W1 ON BRD SMB IN MBCLK10 S1 Figure E-8. CLK10 Generated from MXIbus on a C-Size VXI-MXI-2 MXI Figure E-9. CLK10 Generated from MXIbus on a VXI-MXI-2/B VXIbus Slot 0 The default setting of the VXI-MXI-2 is to automatically detect if it is installed in Slot 0. With automatic detection, you can install the VXI-MXI-2 in any slot of a VXIbus mainframe.
Appendix E Configuring a Two-Frame System VMEbus BTO Unit In each mainframe, the VXI-MXI-2 must be the sole bus timer on the VMEbus regardless of its slot location within the mainframe. Be sure to disable the bus timers on all other modules in the mainframes for proper operation.
Appendix F DMA Programming Examples This appendix contains two example programs for using the DMA controllers on the VXI-MXI-2. If you are using a version of the National Instruments NI-VXI software that has remote DMA controller functionality, this information is not necessary because you can make use of the VXI-MXI-2 module’s DMA controllers from the NI-VXI high-level function calls.
Appendix F DMA Programming Examples Parameter Descriptions The parameters for both functions are ADDRESS_SPACE, ADDRESS, TRANSFER_SIZE, and DATA. • ADDRESS_SPACE represents the VMEbus address space in which the write or read will take place. The examples assume the VXI-MXI-2 is located in A24 space. • ADDRESS represents the address in the memory space to which to perform the write or read. In the examples, A24BASE represents the base A24 address of the VXI-MXI-2.
Appendix F DMA Programming Examples /* The following write causes any block transfer to the MXIbus from either DMA controller to be a synchronous burst transfer by setting both DMAxMBS bits in the SMCR. You can modify this write so that both DMA controllers perform normal MXIbus block transfers, or you can have one DMA controller perform normal MXIbus block transfers and the other perform synchronous burst transfers.
Appendix F DMA Programming Examples /* The following write sets up the base address at which the data will be acquired from the source. Remember that if the source is DRAM onboard the VXI-MXI-2, the offset within the module's space should be written to this register, not the VMEbus address of the source. To compute this value from the source's VMEbus address, just subtract the VXI-MXI-2 module's A24 or A32 base address.
Appendix F DMA Programming Examples /************************************************************ * * * Operation Termination: This section waits for the DMA * * operation to complete. It is important that the * * operation complete before either using the data that * * is being sent to the destination or reprogramming any * * of the DMA registers for another operation.
Appendix F DMA Programming Examples This example adds code to make use of the DMA interrupt functionality on the VXI-MXI-2. Using the interrupt to determine when a DMA operation is complete can improve performance over the polling method described in Example 1 because the read cycles used to poll CHSRx will be using bandwidth on whichever bus (VMEbus or MXIbus) the host is located. The bandwidth the host is using to poll CHSRx will not be available to the VXI-MXI-2 module’s DMA controller.
Appendix F DMA Programming Examples /* The following write is required to initialize the DMAICR. In this example, the DMA interrupt is being routed to VMEbus IRQ5*. You can route the DMA interrupt to any VMEbus interrupt level in the DMAICR. You can put the DMA interrupt on the same level as other interrupt conditions on the VXI-MXI-2 as well as interrupt conditions on other devices. This write is also programming the DMA interrupt condition to use a 16-bit Status ID when being acknowledged.
Appendix F DMA Programming Examples /*********************************************************** * * * Operation setup: This section sets up one of the DMA * * controllers to perform a data transfer from the VMEbus * * to the MXIbus and starts the operation. This process * * should be repeated for each DMA operation. You can also * * perform these steps to the other DMA controller to * * start another operation without waiting for the first * * one to complete.
Appendix F DMA Programming Examples with 0. This step can be skipped if DCR1 was already written with the same value from a previous DMA operation. This is useful if you will be performing several DMA operations where the destination device remains constant. */ write(A24, A24BASE + DCR1, LONGWORD, 0x00E047CB); /* The following write sets up the base address at which the data will be written to the destination.
Appendix F DMA Programming Examples /* The following read generates a 16-bit interrupt acknowledge cycle for level 5 and stores the Status ID returned in the value variable. */ read(IACK, LEVEL5, WORD, value); /* The following if statement checks if the Status ID returned from the interrupt acknowledge cycle matches the code for the VXI-MXI-2 module's DMA interrupt condition (assuming the logical address of the VXI-MXI-2 module is 1).
Appendix F DMA Programming Examples write(A24, A24BASE + DMAIER, BYTE, 0x08); write(A24, A24BASE + CHCR1, LONGWORD, 0x40004000); write(A24, A24BASE + DMAIER, BYTE, 0x09); return_from_interrupt(); } /* DMA controller 2 section */ read(A24, A24BASE + CHSR2, LONGWORD, value); /* The following if statement checks if DMA controller 2 is currently interrupting. */ if (value & 0x80000000) { /* At this point it is known that DMA controller 2 is the interrupter.
Appendix F DMA Programming Examples Table F-1.
Appendix F DMA Programming Examples Table F-1.
Appendix F DMA Programming Examples Table F-1.
Appendix G Mnemonics Key This appendix contains an alphabetical listing of mnemonics used in this manual to describe signals and terminology specific to MXIbus, VMEbus, VXIbus, and register bits. Refer also to the Glossary.
Appendix G Mnemonics Key Mnemonic Type Definition B DMA Status/ID 2 through 0 A16BASE[7:0] B Extender A16 Window Base A16DIR B Extender A16 Window Direction A16EN B Extender A16 Window Enable A16SIZE[2:0] B Extender A16 Window Size A24/A32 ACTIVE B A24/A32 Active A24/A32 ENABLE B A24/A32 Enable A24BASE[7:0] B Extender A24 Window Base A24DIR B Extender A24 Window Direction A24EN B Extender A24 Window Enable A24SIZE[2:0] B Extender A24 Window Size A32BASE[7:0] B Extender
Appendix G Mnemonic Mnemonics Key Type Definition BERR* VBS/MBS Bus Error BLOCKEN B Block Mode DMA BKOFF B Back Off Status BKOFFIE B Back Off Interrupt Enable CHCRx R DMA Channel Control Register CHORx R DMA Channel Operation Register CHSRx R DMA Channel Status Register CLK10 VXS VXIbus 10-MHz System Clock CLR DMAIE B Clear DMA Interrupt Enable CLRDONE B Clear DONE CLR DONEIE B Clear DONE Interrupt Enable CMODE B Comparison Mode CONVERT* MBS Convert DA[31:0] B D
Appendix G Mnemonics Key Mnemonic Type Definition DMAIER R DMA Interrupt Enable Register DMAISIDR R DMA Interrupt Status/ID Register DMAMB S/N* B DMA MXIbus Block Synchronous/Normal DONE B DMA Done DSYSFAIL B Drive SYSFAIL* DSYSFAIL B Drive SYSFAIL* Status DMASID[7:3] B DMA Status/ID 7 through 3 DSYSRST B Drive SYSRESET* DTTRIG[7:0] B Drive VXIbus TTL Trigger Line [7:0] ECL2* B P2 ECL Trigger Support ECL3* B P3 ECL Trigger Support ECLDIR[0] B ECL Trigger [0] Direction
Appendix G Mnemonic Mnemonics Key Type Definition I1[15:0] B Level 1 Interrupter Status ID I2[31:0] B Level 2 Interrupter Status ID I3[15:0] B Level 3 Interrupter Status ID I4[31:0] B Level 4 Interrupter Status ID I5[15:0] B Level 5 Interrupter Status ID I6[31:0] B Level 6 Interrupter Status ID I7[15:0] B Level 7 Interrupter Status ID IACK* VME VMEbus Interrupt Acknowledge ILVL[2:0] B DMA Interrupt Level INT B DMA Interrupt INTDIR[7:1] B Interrupt Direction INTEN[7:1]
Appendix G Mnemonics Key Mnemonic Type Definition MANID[11:0] B Manufacturer ID MBERR B MXIbus Bus Error Status MBTO[3:0] B MXIbus Timeout Value MODEL[11:0] B Model Code MODID* B MODID Line Status MODID[12:0] B MODID Lines MXISC B MXIbus System Controller Status MXSCTO B MXIbus System Controller Timeout Status OFFSET[15:0] B VXIbus Offset OUTEN B MODID Output Enable PAREN B MXIbus Parity Enable PARERR B Parity Error Status PASSED B Passed PORT[1:0] B Port POSTE
Appendix G Mnemonic Mnemonics Key Type Definition S[15:0] B Status ID SA[31:0] B Source Address SABORT B DMA Software Abort SARx R DMA Source Address Register SC[15:0] B Subclass SCFG B Self Configuration Status SCRx R DMA Source Configuration Register SERR[1:0] B Source Error Status SET DMAIE B Set DMA Interrupt Enable SET DONEIE B Set DONE Interrupt Enable SFIE B SYSFAIL* Interrupt Enable SFIN B SYSFAIL* In SFINH B Sysfail Inhibit SFINT B VMEbus SYSFAIL* Inter
Appendix G Mnemonics Key Mnemonic Type Definition TC[31:0] B Transfer Count TCRx R DMA Transfer Count Register TRIG[7:0] B VXIbus TTL Trigger Line [7:0] Status TRIGDIR[7:0] B Trigger Direction TRIGEN[7:0] B Trigger Enable TRIGIN B Trigger In SMB Status TRIGOUT B Trigger Out SMB Status TSIZE[1:0] B Transfer Size TTL* B TTL Trigger Support TTLTRG[7:0] VXI VXIbus TTL Trigger Lines 7 through 0 TTLTRGDIR[7:0] B TTL Trigger Direction TTLTRGEN[7:0] B TTL Trigger Enable B U
Appendix G Mnemonics Key Mnemonic Type Definition VICTR R VXIbus Interrupt Control Register VIDR R VXIbus ID Register VISTR R VXIbus Interrupt Status Register VLAR R VXIbus Logical Address Register VLR R VXIbus Lock Register VMCR R VXI-MXI-2 Control Register VMCR2 R VXI-MXI-2 Control Register 2 VMIDR R VXIbus MODID Register VMSR R VXI-MXI-2 Status Register VMSR2 R VXI-MXI-2 Status Register 2 VMTCR R VXI-MXI-2 Trigger Control Register VOR R VXIbus Offset Register VSCR
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FaxBack Support FaxBack is a 24-hour information retrieval system containing a library of documents on a wide range of technical information. You can access FaxBack from a touch-tone telephone at the following number: (512) 418-1111 E-Mail Support (currently U.S. only) You can submit technical support questions to the appropriate applications engineering team through e-mail at the Internet addresses listed below.
Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item. Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
SMB CLK10 (S7, S6, S3) _________________________________________________________ Receiving or Driving MXIbus CLK10 (S1) ___________________________________________ Trigger Input Termination (S5) _____________________________________________________ MXIbus Termination (U21 switches 3 and 4) __________________________________________ EEPROM Operation (U21 switches 1 and 2) __________________________________________ Onboard DRAM SIMM Size (S2) __________________________________________________ DRAM SIMMs Insta
Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: VXI-MXI-2 User Manual Edition Date: August 1996 Part Number: 371692A-01 Please comment on the completeness, clarity, and organization of the manual. If you find errors in the manual, please record the page numbers and describe the errors. Thank you for your help.
Glossary Prefix Meaning Value n- nano- 10-9 µ- micro- 10-6 m- milli- 10-3 K- kilo- 103 M mega- 106 G- giga- 109 Symbols ° degrees Ω ohms % percent ± plus or minus A A amperes A16 space VXIbus address space equivalent to the VME 64 KB short address space. In VXI, the upper 16 KB of A16 space is allocated for use by VXI devices configuration registers. This 16 KB region is referred to as VXI configuration space.
Glossary A24/A32 Decoder The logic circuit on the VXI-MXI-2 that is responsible for detecting data transfers to the module’s registers or DRAM in A24 or A32 address space. A24 space VXIbus address space equivalent to the VME 16 MB standard address space. A32 space VXIbus address space equivalent to the VME 4 GB extended address space.
Glossary B B bytes backplane An assembly, typically a printed circuit board, with 96-pin connectors and signal paths that bus the connector pins. A C-size VXIbus system will have two sets of bused connectors called J1 and J2. A D-size VXIbus system will have three sets of bused connectors called J1, J2, and J3.
Glossary BTO unit Bus Timeout Unit; a functional module that times the duration of each data transfer and terminates the cycle if the duration is excessive. Without the termination capability of this module, a bus master attempt to access a nonexistent slave could result in an indefinitely long wait for a slave response. bus master A device that is capable of requesting the Data Transfer Bus (DTB) for the purpose of accessing a slave device.
Glossary D daisy-chain A method of propagating signals along a bus, in which the devices are prioritized on the basis of their position on the bus. Data Transfer Bus DTB; one of four buses on the VMEbus backplane. The DTB is used by a bus master to transfer binary data between itself and a slave device. deadlock Unresolved situation in which two devices are vying for the use of a resource.
Glossary EMC Electromechanical Compliance EMI Electromagnetic Interference external controller In this configuration, a plug-in interface board in a computer is connected to the VXI mainframe via one or more VXIbus extended controllers. The computer then exerts overall control over VXIbus system operations. F fair requester A MXIbus master that will not arbitrate for the MXIbus after releasing it until it detects the bus request signal inactive.
Glossary interlocked arbitration mode Contrasted with normal operating mode; an optional mode of operation in which the system performs as one large VXIbus mainframe with only one master of the entire system (VXIbus and MXIbus) at any given moment. In this mode there is no chance for a deadlock situation. interrupt A means for a device to request service from another device.
Glossary M MB Megabytes of memory m meters mainframe extender A device such as the VXI-MXI-2 that interfaces a VXIbus mainframe to an interconnect bus. It routes bus transactions from the VXIbus to the interconnect bus or vice versa. A mainframe extender has a set of registers that defines the routing mechanisms for data transfers, interrupts, triggers, and utility bus signals, and has optional VXIbus Slot 0 capability.
Glossary MTBF Mean Time Between Failure multiframe A system consisting of more than one mainframe connected together to act as one; it can have multiple Slot 0 devices but only one global Resource Manager. MXI-2 The second generation of the National Instruments MXIbus product line. MXI-2 expands the number of signals on a standard MXIbus cable by including VXI triggers, all VXI interrupts, CLK10, SYSFAIL*, SYSRESET*, and ACFAIL*.
Glossary P P1 The minimum connector required for a VMEbus system. It includes 24 address lines, 16 data lines, and all control, arbitration, and interrupt signals. P2 A second VMEbus connector providing 32 bits of address and data. In VXI, the P2 connector adds trigger, MODID, and CLK10 signals. P3 A third connector defined by the VXIbus specification that adds a 100 MHz CLK and additional triggering capabilities. The VXI-MXI-2 does not have support for P3.
Glossary Resource Manager A message-based Commander located at Logical Address 0, which provides configuration management services such as address map configuration, Commander and Servant mappings, and self-test and diagnostic management. response A signal or interrupt generated by a device to notify another device of an asynchronous event. Responses contain the information in the Response register of a sender. RM See Resource Manager.
Glossary slave A functional part of a MXI/VME/VXIbus device that detects data transfer cycles initiated by a VMEbus master and responds to the transfers when the address specifies one of the device’s registers. slave-mode operation A device is in slave mode it if is responding to a bus cycle. Slot 0 device A device configured for installation in Slot 0 of a VXIbus mainframe.
Glossary synchronous communications A communications system that follows the command/response cycle model. In this model, a device issues a command to another device; the second device executes the command and then returns a response. Synchronous commands are executed in the order they are received. Synchronous MXI Block Protocol A block data transfer protocol defined by the MXI-2 specification for high-performance data transfers.
Glossary V V volts VDC volts direct current VME Versa Module Eurocard or IEEE 1014; the IEEE Standard for a Versatile Backplane Bus. VME64 ANSI/VITA 1-1994; defines additional VMEbus protocols such as MBLT and RETRY. VMEbus System Controller A device configured for installation in Slot 0 of a VXIbus mainframe or Slot 1 of a VMEbus chassis.
Index Numbers A16EN bit, 5-14 A16SIZE[2:0] bits, 5-15 A24 address window configuring, 6-44 overview, 2-6 A24/A32 ACTIVE bit, 5-6 A24/A32 decoder, 2-5 A24/A32 ENABLE bit, 5-8 A24/A32 write posting, 7-4 A24BASE[7:0] bits, 5-17 A24DIR bit, 5-17 A24EN bit, 5-16 A24SIZE[2:0] bits, 5-17 A32 address window configuring, 6-44 overview, 2-6 A32BASE[7:0] bits, 5-19 A32DIR bit, 5-19 A32EN bit, 5-18 A32SIZE[2:0] bits, 5-19 ABORT bit, 5-66 ACCDIR bit, 5-7 ACFAIL bit, 5-38 ACFAIL* signal, D-4 ACFIN bit, 5-24 ACFOUT bit,
Index AM[5:0] bits DMA Destination Configuration Register (DCRx), 5-79 DMA Source Configuration Register (SCRx), 5-74 arbiter timeout VMEbus, B-6 VXIbus, 7-9 arbiter type VMEbus, B-6 VXIbus, 7-8 arbitration mode, interlocked, B-9 VXIbus, 7-5 to 7-6 ASCEND bit DMA Destination Configuration Register (DCRx), 5-78 DMA Source Configuration Register (SCRx), 5-73 ASIE bit, D-5 ASINT* bit, D-5 auto retry, configuring MXIbus, 7-12 VXIbus, 7-10 A32DIR, 5-19 A32EN, 5-18 A32SIZE[2:0], 5-19 ABORT, 5-66 ACCDIR, 5-7 ACF
Index EDTYPE[3:0], 5-6 ENABLE, 5-56 ERROR, 5-83 ETOEN, D-5 ETRIG, D-5 ETRIG[1:0], 5-36 FAIR, 5-28, 5-62 FCR[7:0], 5-85 FRESET, 5-66 I1[15:0], 5-43 I2[31:0], 5-44 I3[15:0], 5-45 I4[31:0], 5-46 I5[15:0], 5-47 I6[31:0], 5-48 I7[15:0], 5-49 ILVL[2:0], 5-54 INT, 5-82 INTDIR[7:1], 5-21 INTEN[7:1], 5-20 INTLCK, 5-28, 5-32, 7-6 INTLK, D-5 IOCONFIG, 5-59 IRQ[7:1], 5-38 ISTAT, 5-53 ITS[3:0], D-5 LA[7:0], 5-34 LABASE[7:0], 5-13 LADIR, 5-13 LAEN, 5-12 LASIZE[2:0], 5-13 LINT[3:1], 5-37, 5-39 LNGMXSCTO, D-3 LOCKED, 5-33
Index CLK10 generated from onboard oscillator (figure), 3-8 CLK10 generated from SMB (figure), 3-8 drive inverted external CLK SMB (figure), 3-10 drive non-inverted external CLK SMB (figure), 3-10 receive external CLK SMB (figure), 3-10 receive external CLK SMB with 50 Ω termination (figure), 3-10 receiving or driving MXIbus CLK10 (figure), 3-11 VXI-MXI-2/B, 4-7 to 4-11 CLK10 generated from MXIbus (figure), 4-8 CLK10 generated from onboard oscillator (figure), 4-8 CLK10 generated from SMB (figure), 4-8 dri
Index system configuration. See system configuration. two-frame system. See configuration of two-frame system.
Index DMA Channel Control Register (CHCRx), 5-68 to 5-69 DMA Channel Operation Register (CHORx), 5-65 to 5-67 DMA Channel Status Register (CHSRx), 5-82 to 5-84 DMA controllers 1 and 2, 2-3 DMA Destination Address Register (DARx), 5-80 to 5-81 DMA Destination Configuration Register (DCRx), 5-77 to 5-79 DMA FIFO Count Register (FCRx), 5-85 DMA Interrupt Configuration Register (DMAICR), 5-52 to 5-54 DMA Interrupt Enable Register (DMAIER), 5-55 to 5-56 DMA Interrupt Status/ID Register (DMAISDR), 5-57 to 5-58 D
Index VXI-MXI-2/B Change Factory Configuration switch, 4-14 jumper and switch settings, 4-14 to 4-15 Restore Factory Configuration switch, 4-14 electrical specifications, A-5 electronic support, H-1 to H-2 electrostatic discharge, damage from (warning) VXI-MXI-2, 3-1 VXI-MXI-2/B, 4-1 e-mail support, H-2 ENABLE bit, 5-56 environmental specifications B-size VXI-MXI-2, A-3 C-size VXI-MXI-2, A-3 equipment, optional, 1-5 to 1-6 ERROR bit, 5-83 ETOEN bit, D-5 ETRIG bit, D-5 ETRIG[1:0] bits, 5-36 Extender A16 Win
Index J I7[15:0] bits, 5-49 ILVL[2:0] bits, 5-54 installation. See also configuration.
Index LNGMXSCTO bit, D-3 local bus configuration, VXIbus VXI-MXI-2, 3-6 to 3-7 VXI-MXI-2/B, 4-6 to 4-7 local interrupt conditions, D-4 to D-5 LOCKED bit, 5-33 logical address, VXIbus configuring for two-frame system, E-4 to E-5 VXI-MXI-2, 3-3 to 3-4 VXI-MXI-2/B, 4-3 to 4-4 decoder, 2-5 definition, 3-3, 4-3 logical address, VXIplug&play Logical Address control, 7-3 Logical Address Selection control, 7-3 logical address (LA) window configuring, 6-39 to 6-40 example, 6-40 to 6-43 logical address assignments f
Index mnemonics key, G-1 to G-9 MODEL[11:0] bits, 5-5 MODID* bit, 5-6 MODID[12:0]bits, 5-11 multiframe RM multiframe RM in VXIbus mainframe (figure), 6-3 multiframe RM on PC (figure), 6-2 overview, 6-1 tree topologies, 6-1 multiframe RM operation, 6-39 to 6-44 configuring A24 and A32 addressing windows, 6-44 configuring logical address window, 6-39 to 6-40 example, 6-40 to 6-43 logical address assignments for example VXIbus/MXIbus system (table), 6-41 system administration and initiation, 6-44 MXACFAILEN b
Index configuration, VXI-MXI-2/B, 4-16 to 4-17 SIMM size configuration (figure), 4-16 VXI-MXI-2/B DRAM configurations (table), 4-17 overview, 2-7 optional equipment for VXI-MXI-2, 1-5 to 1-6 OTS[3:0] bits, D-5 OUTEN bit, 5-11 requested memory space, VXI-MXI-2, B-3 to B-4 requester, VMEbus, B-7 reset, hard and soft, 5-1, D-5 RESET bit soft resets, 5-1 VXIbus Control Register (VCR), 5-9 VXIbus Status Register (VSR), 5-7 RM operation, multiframe. See multiframe RM operation.
Index slave state machine MXI-2, 2-5 VMEbus, 2-4 Slot 0, VXIbus configuring two-frame system, E-8 VXI-MXI-2, 3-5 to 3-6 VXI-MXI-2/B, 4-5 to 4-6 functions, 2-3 reconfiguring for Slot 0 devices placed in another slot (warning) VXI-MXI-2, 3-5 VXI-MXI-2/B, 4-5 SMB transceivers, 2-7 soft reset of registers, 5-1, D-5 specifications electrical, A-5 environmental, A-3 MXIbus capability descriptions, A-1 performance, A-5 physical, A-4 requirements, A-4 VMEbus capability codes, A-2 SRIN bit, 5-25 SROUT bit, 5-25 SSI
Index multiframe RM in VXIbus mainframe (figure), 6-3 multiframe RM on PC (figure), 6-2 required logical addresses for example VXIbus/MXIbus system (table), 6-7 steps to follow, 6-6 to 6-11 worksheets for VXIbus/MXIbus A16 address map A16 space address map diagram, 6-33 MXIbus #1 A16 address map, 6-35 MXIbus #1 of example A16 address map, 6-30 to 6-31 MXIbus #2 A16 address map, 6-36 MXIbus #3 A16 address map, 6-37 MXIbus #3 of example A16 address map, 6-32 MXIbus #4 A16 address map, 6-38 summary of A16 add
Index V transfer limit, configuring MXIbus, 7-11 VXIbus, 7-9 TRGIN bit, 5-36 TRGOUT bit, 5-36 TRIG[7:0] bits, 5-34 TRIGDIR[7:0] bits, 5-42 TRIGEN[7:0] bits, 5-42 trigger circuitry, CLK10, 2-7 trigger input connector, C-8 TRG IN connector (figure), C-8 TRG IN signal characteristics (table), C-8 trigger output connector, C-7 TRG OUT (figure), C-7 TRG OUT signal characteristics (table), C-7 triggers CLK10 and trigger transceivers, 2-7 CLK10 and TTL and ECL trigger transceivers, 2-7 input termination VXI-MXI-
Index DMA Source Address Register (SARx), 5-75 to 5-76 DMA Source Configuration Register (SCRx), 5-72 to 5-74 DMA Transfer Count Register (TCRx), 5-70 to 5-71 hard and soft reset, 5-1, D-5 mnemonics key, G-1 to G-9 register map (table), 5-51 Shared MXIbus Status/Control Register (SMSR/SMCR), 5-61 to 5-64 VXI-MXI-2 Status/Control Register 2 (VMSR2/VMCR2), 5-59 to 5-60, D-3 to D-5 VXIbus Bus Timeout (BTO), 7-8 VXIbus CLK10 and TTL and ECL trigger transceivers, 2-7 VXIbus configuration two-frame system CLK10
Index VXIbus Trigger Drive Register (VTDR), 5-35, D-5 VXIbus Trigger Mode Select Register (VTMSR), 5-36 VXIbus TTL Trigger Configuration Register (VTCR), 5-22 VXIbus Utility Configuration Register (VUCR), 5-23 to 5-25 VXI-MXI-2 Control Register (VMCR), 5-30 to 5-32, D-4 VXI-MXI-2 Status Register (VMSR), 5-27 to 5-29, D-4 VXI-MXI-2 Trigger Control Register (VMTCR), 5-42 VXIbus logical address. See logical address, VXIbus.
Index VXIbus settings arbiter timeout, 7-9 arbiter type, 7-8 auto retry, 7-10 bus timeout, 7-8 fair requester, 7-9 illustration, 7-7 request level, 7-9 System Controller, 7-7 to 7-8 transfer limit, 7-9 VXIplug&play soft front panel. See VXI-MXI-2 VXIplug&play soft front panel.