User manual

Chapter 5 Register Descriptions
VXI-MXI-2 User Manual 5-32 © National Instruments Corporation
10 ECLDIR[0] ECL Trigger [0] Direction
When the ECLEN[0] bit is clear, this bit is
ignored. When the ECLEN[0] bit is set, this bit
controls the direction in which the trigger is
routed. The trigger is routed from the VXIbus to
the TRG OUT SMB connector when ECLDIR[0]
is 0 (outward), and from the TRG IN SMB
connector to the VXIbus when ECLDIR[0] is 1
(inward). This bit is cleared by a hard reset and is
not affected by a soft reset.
9 DSYSFAIL Drive SYSFAIL*
Writing a 1 to this bit causes the VXI-MXI-2 to
assert the VMEbus SYSFAIL* line. This bit is
cleared by hard and soft resets.
8 DSYSRST Drive SYSRESET*
Writing a 1 to this bit causes the VXI-MXI-2 to
assert the VMEbus SYSRESET* line for a
minimum of 200 ms. This bit is automatically
cleared after the assertion of SYSRESET*.
7-1 0 Reserved
These bits are reserved. Write each of these bits
with 0 when writing to the VMCR.
0 INTLCK Interlocked Mode
Writing a 1 to this bit causes the VXI-MXI-2 to
interlock arbitration between the VXIbus and the
MXIbus. When arbitration is interlocked, the
VXI-MXI-2 will always own either the VXIbus
or the MXIbus. When the VXI-MXI-2 must
release the bus that it owns, it does not do so
until it obtains ownership of the other bus
(VXIbus or the MXIbus). If the VXI-MXI-2
does not own either bus when this bit is written
with a 1, it will arbitrate for the VXIbus. This bit
is cleared by a hard reset and is not affected by a
soft reset. Refer to Chapter 7, VXIplug&play for
the VXI-MXI-2, for more detailed information on
interlocked mode.