User manual

Chapter 5 Register Descriptions

VXIbus Lock Register (VLR)

VXIbus Configuration Offset: 22 (hex)

Attributes: Read/Write 16, 8-bit accessible

15 14 13 12 11 10 9 8

11 11 111 1

76 54 321 0

1 1 1 1 1 1 1 LOCKED

This register is used to lock the VXIbus or the MXIbus. This register performs differently

depending on whether the register is accessed from the VXIbus or the MXIbus.

Bit Mnemonic Description

15-1 1 Reserved

These bits are reserved and each returns 1 when

read. Write a 0 to each of these bits when writing

to the VLR.

0 LOCKED VXIbus or MXIbus Locked

When this bit is set by a VXIbus access, the

VXI-MXI-2 arbitrates for the MXIbus. Once the

VXI-MXI-2 wins arbitration, it does not give up

ownership of the MXIbus until either this bit is

cleared or a reset occurs. This prevents any other

MXIbus masters from using the bus so that the

VXI-MXI-2 can complete indivisible operations.

When this bit is set by a MXIbus access, the

VXIbus is locked by that device so that

indivisible operations to local VXIbus resources

can be performed from the MXIbus. Similarly,

when a VXIbus device reads this bit as a 1, it

indicates that the MXIbus is locked. When a

MXIbus device reads this bit as a 1, it indicates

that the VXIbus is locked. This bit does not read

as a 1 until the VXI-MXI-2 has successfully

arbitrated for and won the indicated bus. Writing

a 0 to this bit unlocks the appropriate bus. This

bit is cleared by hard and soft resets.