User manual

Chapter 5 Register Descriptions
VXI-MXI-2 User Manual 5-34 © National Instruments Corporation
VXIbus Logical Address Register (VLAR)
VXIbus Configuration Offset: 26 (hex)
Attributes: Read Only 16, 8-bit accessible
15 14 13 12 11 10 9 8
TRIG[7] TRIG[6] TRIG[5] TRIG[4] TRIG[3] TRIG[2] TRIG[1] TRIG[0]
76 54 321 0
LA[7] LA[6] LA[5] LA[4] LA[3] LA[2] LA[1] LA[0]
This register provides the logical address of the VXI-MXI-2. It also allows monitoring of
the VXIbus TTL trigger [7:0] lines.
Bit Mnemonic Description
15-8 TRIG[7:0] VXIbus TTL Trigger Line [7:0] Status
These bits return the current state of the eight
VXIbus TTL trigger lines on the mainframe. If a
bit returns a 1, the corresponding TTL trigger is
asserted.
7-0 LA[7:0] Logical Address Status
These bits return the logical address of the
VXI-MXI-2.