User manual

Chapter 5 Register Descriptions

VXIbus Trigger Drive Register (VTDR)

VXIbus Configuration Offset: 26 (hex)

Attributes: Write Only 16, 8-bit accessible

15 14 13 12 11 10 9 8

DTTRIG[7] DTTRIG[6] DTTRIG[5] DTTRIG[4] DTTRIG[3] DTTRIG[2] DTTRIG[1] DTTRIG[0]

76 54 321 0

0 0 0 0 0 0 DETRIG[1] DETRIG[0]

This register allows the VXI-MXI-2 to assert the VXIbus TTL and ECL trigger lines.

Bit Mnemonic Description

15-8 DTTRIG[7:0] Drive VXIbus TTL Trigger Line [7:0]

Writing a 1 to one of these bits causes the

VXI-MXI-2 to assert the corresponding VXIbus

TTL trigger line. These bits are cleared by a hard

reset and are not affected by a soft reset. The

state of the VXIbus TTL trigger lines can be

monitored in the VXIbus Logical Address

7-2 0 Reserved

These bits are reserved. Write a 0 to each of

these bits when writing the VTDR.

1-0 DETRIG[1:0] Drive VXIbus P2 ECL Trigger Line [1:0]

Writing a 1 to one of these bits causes the

VXI-MXI-2 to assert the corresponding VXIbus

P2 ECL trigger line. These bits are cleared by a

hard reset and are not affected by a soft reset.

The state of the VXIbus P2 ECL trigger lines can

be monitored in the VXIbus Trigger Mode Select