User manual

Chapter 5 Register Descriptions
VXI-MXI-2 User Manual 5-36 © National Instruments Corporation
VXIbus Trigger Mode Select Register (VTMSR)
VXIbus Configuration Offset: 28 (hex)
Attributes: Read Only 16, 8-bit accessible
15 14 13 12 11 10 9 8
11 11 111 1
76 54 321 0
ETRIG[1] ETRIG[0] 1 1 TRGIN TRGOUT 1 1
You can use this register to monitor the VXIbus P2 ECL trigger [1:0] lines as well as the
front-panel SMB connector triggers.
Bit Mnemonic Description
15-8 1 Reserved
These bits are reserved and each returns 1 when
read.
7-6 ETRIG[1:0] VXIbus P2 ECL Trigger Line [1:0] Status
These bits return the current state of the two
VXIbus P2 ECL trigger lines on the mainframe.
If a bit returns a 1, the corresponding ECL
trigger is asserted.
5-4 1 Reserved
These bits are reserved and each returns 1 when
read.
3 TRGIN Trigger In SMB Status
This bit returns the current state of the front-
panel TRG IN SMB connector. A 1 indicates that
the input signal is high, while a 0 indicates the
signal is low.
2 TRGOUT Trigger Out SMB Status
This bit returns the current state of the front-
panel TRG OUT SMB connector. A 1 indicates
that the output signal is high, while a 0 indicates
the signal is low.
1-0 1 Reserved
These bits are reserved and each returns 1 when
read.