User manual

Chapter 5 Register Descriptions
VXI-MXI-2 User Manual 5-38 © National Instruments Corporation
10 0 Reserved
This bit is reserved and returns 0 when read.
9 SYSFAIL SYSFAIL* Status
This bit returns the current state of the VMEbus
SYSFAIL* signal. A 1 indicates that SYSFAIL*
is asserted (low), while a 0 indicates it is not
asserted (high). If the SFIE bit in the VXIbus
Interrupt Control Register (VICTR) is set, an
interrupt is also generated when SYSFAIL*
asserts.
8 ACFAIL ACFAIL* Status
This bit returns the current state of the VMEbus
ACFAIL* signal. A 1 indicates that ACFAIL* is
asserted (low), while a 0 indicates it is not
asserted (high). If the AFIE bit in the VXIbus
Interrupt Control Register (VICTR) is set, an
interrupt is also generated when ACFAIL*
asserts.
7 SFINT VMEbus SYSFAIL* Interrupt Status
This bit returns 1 when the VXI-MXI-2 is
driving the VMEbus IRQ[7:1] selected by
LINT[3:1] because the SYSFAIL* line is
asserted. This bit clears after the VXI-MXI-2
responds to an interrupt acknowledge cycle for
the local interrupt. The SYSFAIL* interrupt is
enabled with the SFIE bit in the VXIbus
Interrupt Control Register (VICTR).
6-0 IRQ[7:1] VMEbus Interrupt Request [7:1] Status
These bits return the current state of the seven
VMEbus interrupt request lines on the
mainframe. If a bit returns a 1, the corresponding
IRQ is asserted.