User manual

Chapter 5 Register Descriptions
VXI-MXI-2 User Manual 5-40 © National Instruments Corporation
9 SFIE SYSFAIL* Interrupt Enable
Writing a 1 to this bit enables the SFINT
interrupt condition in the VXIbus Interrupt
Status Register (VISTR) to assert the VMEbus
IRQ[7:1] selected by LINT[3:1]. This bit is
cleared by a hard reset and is not affected by a
soft reset.
8 AFIE ACFAIL* Interrupt Enable
Writing a 1 to this bit enables the AFINT
interrupt condition in the VXIbus Interrupt
Status Register (VISTR) to assert the VMEbus
IRQ[7:1] selected by LINT[3:1]. This bit is
cleared by a hard reset and is not affected by a
soft reset.
7 0 Reserved
This bit is reserved. Write a 0 when writing to
this bit.
6-0 DIRQ[7:1] Drive VMEbus Interrupt Request [7:1]
Writing a 1 to one of these bits causes the
VXI-MXI-2 to assert the corresponding VMEbus
interrupt request. When the interrupt driven from
these bits is acknowledged, the value in the
VXIbus Status ID Register (VSIDR) is returned
and the DIRQ[7:1] bit clears, releasing the
interrupt. These bits are cleared by a hard reset
and are not affected by a soft reset. The state of
the VMEbus interrupt request lines can be
monitored in the VXIbus Interrupt Status
Register (VISTR).