User manual

Chapter 5 Register Descriptions

VXIbus Status ID Register (VSIDR)

VXIbus Configuration Offset: 2C (hex)

Attributes: Read/Write 16, 8-bit accessible

15 14 13 12 11 10 9 8

S[15] S[14] S[13] S[12] S[11] S[10] S[9] S[8]

76 54 321 0

S[7] S[6] S[5] S[4] S[3] S[2] S[1] S[0]

This register contains the Status ID value, which is returned during an interrupt

acknowledge cycle for an IRQ[7:1] line that is being driven with the DIRQ[7:1] bits in

the VXIbus Interrupt Control Register (VICTR).

Bit Mnemonic Description

15-0 S[15:0] Status ID

These bits are cleared by a hard reset and are not

affected by a soft reset.