User manual

Chapter 5 Register Descriptions
VXI-MXI-2 User Manual 5-46 © National Instruments Corporation
VXIbus Interrupt Acknowledge Register 4 (VIAR4)
VXIbus Configuration Offset: 38 (hex)
Attributes: Read Only 32, 16, 8-bit accessible
31 30 29 28 27 26 25 24
I4[31] I4[30] I4[29] I4[28] I4[27] I4[26] I4[25] I4[24]
23 22 21 20 19 18 17 16
I4[23] I4[22] I4[21] I4[20] I4[19] I4[18] I4[17] I4[16]
15 14 13 12 11 10 9 8
I4[15] I4[14] I4[13] I4[12] I4[11] I4[10] I4[9] I4[8]
76 54 321 0
I4[7] I4[6] I4[5] I4[4] I4[3] I4[2] I4[1] I4[0]
This register generates a VXIbus Interrupt Acknowledge (IACK) cycle for interrupt level
4 when read from the MXIbus and returns the Status ID received from the interrupter. It
can generate 32-bit, 16-bit, or 8-bit IACK cycles. Generating an 8-bit IACK cycle
requires reading offset 39 (hex). When read from the VXIbus, this register does not
generate an IACK cycle and returns FFFFFFFF (hex).
Bit Mnemonic Description
31-0 I4[31:0] Level 4 Interrupter Status ID
These bits return the Status ID received during
the IACK cycle.