User manual

Chapter 5 Register Descriptions

VXIbus Interrupt Acknowledge Register 5 (VIAR5)

VXIbus Configuration Offset: 3A (hex)

Attributes: Read Only 16, 8-bit accessible

15 14 13 12 11 10 9 8

I5[15] I5[14] I5[13] I5[12] I5[11] I5[10] I5[9] I5[8]

76 54 321 0

I5[7] I5[6] I5[5] I5[4] I5[3] I5[2] I5[1] I5[0]

This register generates a VXIbus Interrupt Acknowledge (IACK) cycle for interrupt level

5 when read from the MXIbus and returns the Status ID received from the interrupter. It

can generate 16-bit or 8-bit IACK cycles. Generating an 8-bit IACK cycle requires

reading offset 3B (hex). When read from the VXIbus, this register does not generate an

IACK cycle and returns FFFF (hex).

Bit Mnemonic Description

15-0 I5[15:0] Level 5 Interrupter Status ID

These bits return the Status ID received during

the IACK cycle.