User manual

Chapter 5 Register Descriptions
© National Instruments Corporation 5-53 VXI-MXI-2 User Manual
14 SIDLA Logical Address Status/ID
When the SID8 bit is set, this bit selects what
information is provided during IACK cycles for
the DMA interrupt. This bit should not be set
when SID8 is clear. When this bit is set, the
logical address of the VXI-MXI-2 is used as the
Status/ID information. When this bit is clear, the
contents of the DMAISIDR are used. This bit is
cleared on a hard reset and is not affected by a
soft reset.
13 1 Reserved
This bit is reserved. It must be initialized to 1 for
the DMA interrupt to operate properly. This bit
is cleared on a hard reset and is not affected by a
soft reset.
12 0 Reserved
This bit is reserved. Write this bit with 0 when
writing the DMAICR. The value this bit returns
when read is meaningless.
11 1 Reserved
This bit is reserved. It must be initialized to 1 for
the DMA interrupt to operate properly. This bit
is cleared on a hard reset and is not affected by a
soft reset.
10-8 0 Reserved
These bits are reserved. Write each of these bits
with 0 when writing the DMAICR. The value
these bits return when read is meaningless.
7 ISTAT DMA Interrupt Status bit
This read-only bit indicates the status of the
DMA interrupt. When this bit returns 1, it means
that the interrupt condition is present. Once the
condition is present, it will remain until
re-armed. Notice that even though the
VXI-MXI-2 releases the IRQ* line on the
VXIbus during the IACK cycle, the IACK cycle
does not clear this status bit. See Appendix F,
DMA Programming Examples, for more
information on re-arming the DMA interrupt.