User manual

Chapter 5 Register Descriptions

DMA Interrupt Status/ID Register (DMAISIDR)

VXIbus A24 or A32 Offset: 20 (hex)

Attributes: Read/Write 16, 8-bit accessible

15 14 13 12 11 10 9 8

00 00 000 0

76 54 321 0

DMASID[7] DMASID[6] DMASID[5] DMASID[4] DMASID[3] 0 1 1

This register provides the Status/ID information during IACK cycles for the DMA

interrupt. If SID8 and SIDLA are both set in the DMA Interrupt Configuration Register

(DMAICR), only the VXI-MXI-2 module’s logical address is provided and this register

is not used. If SID8 is clear in the DMAICR (16-bit Status/ID) this register provides the

upper 8 bits of the Status/ID and the VXI-MXI-2 module’s logical address is placed on

the lower 8 bits.

Bit Mnemonic Description

15-8 0 Reserved

These bits are reserved. Write each of these bits

with 0 when writing the DMAISIDR. The value

these bits return when read is meaningless.

7-3 DMASID[7:3] DMA Status/ID 7 through 3

These bits can be written with any value to

uniquely identify the DMA interrupt during an

IACK cycle. When SID8 is clear in the

DMAICR (16-bit Status/ID), these bits provide

bits 15 through 11 of the Status/ID. When SID8

is set (8-bit Status/ID) and SIDLA is clear in the

DMAICR, these bits provide bits 7 through 3 of

the Status/ID. These bits are cleared on a hard

reset and are not affected by a soft reset.