User manual

Chapter 5 Register Descriptions

VXI-MXI-2 Status/Control Register 2 (VMSR2/VMCR2)

VXIbus A24 or A32 Offset: 758 (hex)

Attributes: Read/Write 32, 16, 8-bit accessible

31 30 29 28 27 26 25 24

00 00 000 0

23 22 21 20 19 18 17 16

00 00 000 0

15 14 13 12 11 10 9 8

00 00 000 0

76 54 321 0

IOCONFIG 0 0 0 0 0 0 1

This register enables access to the VXI-MXI-2 onboard EEPROM. For more information

on changing configuration settings in the EEPROM, refer to Appendix B, Programmable

Configurations.

Bit Mnemonic Description

31-8 0 Reserved

These bits are reserved. Write these bits with 0

when writing the VMCR2.

7 IOCONFIG I/O Configuration Space Enable

This bit controls accesses to I/O configuration

space (the onboard EEPROM). A device

requesting access to the I/O configuration space

must set this bit. When this bit is set, any

accesses through the A24/A32 inward window

that would normally map to the onboard DRAM

(address offsets above FFF hex) instead map to

the configuration space, accessing the EEPROM.

On completion of configuration activity, the

master should then clear this bit. Notice that this

bit cannot be locked. The master must ensure

that it is the only device accessing VXI-MXI-2

address offsets above FFF (hex) while this bit is

set. This bit is cleared on a hard reset and is not

affected by a soft reset.