User manual

Chapter 5 Register Descriptions
© National Instruments Corporation 5-63 VXI-MXI-2 User Manual
20-19 0 Reserved
These bits are reserved. Write these bits with 0
when writing to the SMCR.
18 PAREN MXIbus Parity Enable
Setting this bit enables the checking of MXIbus
parity. When this bit is clear, the VXI-MXI-2
does not check MXIbus parity. Refer to
Chapter 7, VXIplug&play for the VXI-MXI-2,
or Appendix B, Programmable Configurations,
for more information on MXIbus parity
checking. On a hard reset, this bit is initialized
to the value stored in the onboard EEPROM for
this bit.
17 0 Reserved
This bit is reserved. Write this bit with 0 when
writing to the SMCR.
16 1 Reserved
This bit is reserved. Write this bit with 1 when
writing to the SMCR.
15-9 0 Reserved
These bits are reserved. Write these bits with 0
when writing to the SMCR.
8 1 Reserved
This bit is reserved. Write this bit with 1 when
writing to the SMCR.
7-4 0 Reserved
These bits are reserved. Write these bits with 0
when writing to the SMCR.
3-0 MBTO[3:0] MXIbus Timeout Value
The MBTO[3:0] bits determine the amount
of time the VXI-MXI-2 will wait before
terminating a MXIbus cycle by asserting BERR*
when acting as the MXIbus System Controller.