User manual

Chapter 5 Register Descriptions

DMA Channel Operation Register (CHORx)

CHOR1 VXIbus A24 or A32 Offset: D00 (hex)

CHOR2 VXIbus A24 or A32 Offset: E00 (hex)

Attributes: Read/Write 32, 16, 8-bit accessible

31 30 29 28 27 26 25 24

00 00 000 0

23 22 21 20 19 18 17 16

00 00 000 0

15 14 13 12 11 10 9 8

00 00 000 0

76 54 321 0

CLRDONE 0 0 FRESET ABORT STOP 0 START

This register is used to control overall operation of the DMA controller, such as starting a

transfer after all the other DMA registers have been programmed.

Bit Mnemonic Description

31-8 0 Reserved

These bits are reserved. Write each of these bits

with 0 when writing the CHORx. The value

these bits return when read is meaningless.

7 CLRDONE Clear DONE

This bit can be written with a 1 to clear the

DONE bit in the DMA Channel Status Register

(CHSRx). The DONE bit also clears

automatically when a new DMA operation is

started. It is not necessary to clear the

CLRDONE bit after writing a 1 to it.

6-5 0 Reserved

These bits are reserved. Write each of these bits

with 0 when writing the CHORx. The value

these bits return when read is meaningless.