User manual

Chapter 5 Register Descriptions

VXI-MXI-2 User Manual 5-68 © National Instruments Corporation

DMA Channel Control Register (CHCRx)

CHCR1 VXIbus A24 or A32 Offset: D04 (hex)

CHCR2 VXIbus A24 or A32 Offset: E04 (hex)

Attributes: Read/Write 32, 16, 8-bit accessible

31 30 29 28 27 26 25 24

SET DMAIE CLR DMAIE 0 0 0 0 SET DONEIE CLR DONEIE

23 22 21 20 19 18 17 16

00 00 000 0

15 14 13 12 11 10 9 8

01 00 000 0

76 54 321 0

00 00 000 0

This register is used to individually enable the two DMA controllers to assert the DMA

interrupt. Because the DMA interrupt is shared between the two DMA controllers, this

Bit Mnemonic Description

31 SET DMAIE Set DMA Interrupt Enable

Writing a 1 to this bit enables the corresponding

DMA controller to assert the DMA interrupt.

Writing a 0 to this bit has no effect. This bit

returns a 1 when read if the corresponding DMA

controller is enabled to assert the interrupt and a

0 if it is disabled. The interrupt is disabled by a

hard reset and is not affected by a soft reset.

30 CLR DMAIE Clear DMA Interrupt Enable

Writing a 1 to this bit disables the corresponding

DMA controller from asserting the DMA

interrupt. Writing a 0 to this bit has no effect.

This bit returns a 0 when read if the

corresponding DMA controller is enabled to

assert the interrupt and a 1 if it is disabled. The

interrupt is disabled by a hard reset and is not

affected by a soft reset.