User manual

Chapter 5 Register Descriptions
© National Instruments Corporation 5-73 VXI-MXI-2 User Manual
14 BLOCKEN Block Mode DMA
Write a 1 to this bit to cause the DMA controller
to perform block-mode transfers to the source.
During block mode, the DMA controller keeps
the AS* signal asserted throughout a series of
read cycles to the source. The DMA controller
automatically deasserts and reasserts the AS*
signal when it reaches the appropriate transfer
size limit for the bus on which the source is
located (for example 256 bytes on the VXIbus).
In addition, if the corresponding DMAxMBS bit
is set in the Shared MXIbus Control Register
(SMCR), any block-mode cycles from the DMA
controller to the MXIbus are performed as a
synchronous burst cycle. When this bit is clear,
the DMA controller performs a series of standard
single read cycles to the source deasserting the
AS* signal after each cycle. This bit is cleared
by a hard reset and is not affected by a soft reset.
13-11 0 Reserved
These bits are reserved. Write each of these bits
with 0 when writing the SCRx. The value these
bits return when read is meaningless.
10 ASCEND Ascending Addresses
Write a 1 to this bit to cause the DMA controller
to increment the source address between each
data transfer of the DMA operation. The source
address is incremented by 1, 2, 4, or 8—
depending on the width of the source data
transfers—resulting in the DMA controller
accessing locations on the source in ascending
order. When this bit is clear, the DMA controller
does not increment the source address
throughout the DMA operation, resulting in all
the data coming from the same location on the
source. This bit is cleared by a hard reset and is
not affected by a soft reset.