User manual

Chapter 5 Register Descriptions
VXI-MXI-2 User Manual 5-84 © National Instruments Corporation
8-4 0 Reserved
These bits are reserved. The value these bits
return when read is meaningless.
3-2 SERR[1:0] Source Error Status
These bits indicate the type of error that occurred
when accessing the source. When 00 (binary) is
returned, no error occurred. When 01 (binary) is
returned, a data transfer to the source got a bus
error. When 10 (binary) is returned, it indicates
that the retry limit was exceeded trying to access
the source. The DMA controller retries up to 64
times any data transfer that receives a RETRY*
acknowledge. If the data transfer receives a
RETRY* acknowledge for the 65th time, the
DMA controller terminates the operation and
sets the retry limit exceeded status in the
SERR[1:0] bits. When 11 (binary) is returned, it
indicates that a data cycle to the source got a
MXIbus parity error.
1-0 DERR[1:0] Destination Error Status
These bits indicate the type of error that occurred
when accessing the destination. When 00
(binary) is returned, no error occurred. When 01
(binary) is returned, a data transfer to the
destination got a bus error. When 10 (binary) is
returned, it indicates that the retry limit was
exceeded trying to access the destination. The
DMA controller will retry up to 64 times any
data transfer that receives a RETRY*
acknowledge. If the data transfer receives a
RETRY* acknowledge for the 65th time, the
DMA controller terminates the operation and
sets the retry limit exceeded status in the
DERR[1:0] bits.