User manual

Chapter 1 Introduction

The VXI-MXI-2 converts A32, A24, A16, D64, D32, D16, and

D08(EO) VXIbus bus cycles into MXIbus bus cycles and vice versa.

The VXI-MXI-2 has four address windows that map into and out of the

VXIbus mainframe. These four windows represent the three VMEbus

address spaces (A32, A24, and A16) plus a dedicated window for

mapping the VXIbus configuration space (the upper 16 KB of A16

space).

The MXIbus is a multidrop system bus that connects multiple devices

at the hardware bus level in a software-transparent manner. You can

connect multiple VXIbus mainframes using VXI-MXI-2 interfaces to

form a single multiframe VXIbus system. You can also connect an

external PC with a MXIbus interface to a VXIbus mainframe with a

VXI-MXI-2. This configuration makes the PC function as though it

were an embedded VXIbus controller that is plugged into the VXIbus

mainframe.

Multiple MXIbus devices are tightly coupled by mapping together

portions of each device’s address space and locking the internal

hardware bus cycles to the MXIbus. The window address circuitry on

each MXIbus device monitors internal local bus cycles to detect bus

cycles that map across the MXIbus. Similarly, external MXIbus cycles

are monitored to detect MXIbus cycles that map into the VXIbus

system. MXIbus devices can operate in parallel at full speed over their

local system bus and need to synchronize operation with another device

only when addressing or being addressed by a resource located on

another MXIbus device. The MXIbus device originating the transaction

must gain ownership of both the MXIbus and the local bus in the target

MXIbus device. All hardware bus cycles are then coupled across the

MXIbus and local buses before the transfer completes.

The VXI-MXI-2 has the following features:

• Interfaces the VXIbus to the MXIbus (32-bit Multisystem

eXtension Interface bus)

• Extends VXIbus to multiple mainframes, external MXIbus-

equipped instruments, and external MXIbus-equipped PCs

• Allows multiple VXIbus mainframes to operate as a single VXIbus

system

• Supports the VME RETRY* signal to resolve deadlock conditions

• Supports D64, block, and synchronous MXI cycles for high-

performance data transfer

• Two independent DMA controllers for data transfer