User manual

Programmable

Configurations

Appendix

This appendix describes some features of the VXI-MXI-2 that are

configured by programming an onboard EEPROM through software

rather than by onboard switches or jumpers.

Configuring the EEPROM

The EEPROM settings are loaded into the VXI-MXI-2 registers after

each power-up or hard reset. The VXI-MXI-2 must be reset either with

a power cycle or by asserting the VMEbus SYSRESET* signal after

the EEPROM is written for the changes to take effect. The EEPROM

retains its settings even when power is removed from the VXI-MXI-2.

Once you program the settings into the EEPROM, they need not be

programmed again unless you want to make further changes to the

settings.

The EEPROM is accessible in the VXI-MXI-2 A24 or A32 memory

region defined by the VIDR, VDTR, VCR, and VOR registers. It is

required that when the Resource Manager executes, it allocates A24 or

A32 space to the VXI-MXI-2 before the EEPROM can be accessed.

If you are not using a multiframe VXIbus Resource Manager, you must

allocate A24 or A32 space to the VXI-MXI-2 by writing a base address

to the VOR and then setting the A24/A32 ENABLE bit in the VCR.

The space (either A24 or A32) and amount of address space that the

VXI-MXI-2 requires can be determined by reading the VIDR

and VDTR. Following this allocation, the IOCONFIG bit in the

VXI-MXI-2 Control Register 2 (VMCR2) must be written with a

1 before the EEPROM is accessible. The IOCONFIG bit should be

written with a 0 after accesses to the EEPROM are complete to

prevent unintentional accesses to the EEPROM.

The EEPROM must be written with 8-bit accesses. Also, after each

write access to the EEPROM, the location written should be

continuously read back until the value written is returned before

attempting any further write accesses.