User manual

Appendix B Programmable Configurations

MXIbus Fair Requester and MXIbus Parity Checking

You can configure whether the VXI-MXI-2 acts as either a fair or

unfair requester on the MXIbus. The default is a fair requester, which

causes the VXI-MXI-2 to request the MXIbus only when there are no

requests pending from other masters. This prevents other masters from

being starved of bandwidth. The VXI-MXI-2 will request the bus at

any time when configured for unfair operation.

MXIbus parity checking can also be disabled in the same EEPROM

location as the MXIbus fair requester setting. By default, MXIbus

parity checking is enabled and should not be disabled under normal

circumstances. MXIbus parity is always generated regardless if

checking is enabled or disabled.

To change the MXIbus requester type or the MXIbus parity checking

setting of the VXI-MXI-2, write the EEPROM byte at offset 2065 hex

from the VXI-MXI-2 base address. The following table gives the value

that should be written for the corresponding requester type and parity

checking combination.

Parity Checking Status Fair Requester Unfair Requester

Parity Checking Enabled E5 (default) C5

Parity Checking Disabled E1 C1

Interlocked Arbitration Mode

Interlocked arbitration mode is an optional mode of operation in which

at any given moment the system can perform as if it were one large

VXIbus mainframe with only one master of the entire system—VXIbus

and MXIbus. This mode of operation prevents deadlocks by

interlocking all arbitration in the VXIbus/MXIbus system.

To change the arbitration mode of the VXI-MXI-2, the EEPROM bytes

at offsets 2035 and 2037 must be written. Write a 0 to each location for

normal arbitration mode, or write a 1 to each location for interlocked

arbitration mode.

For more information on interlocked mode, refer to Chapter 7,

VXIplug&play for the VXI-MXI-2.