User manual

Appendix D Differences and Incompatibilities between the VXI-MXI and the VXI-MXI-2

Configurable Feature VXI-MXI-2 Implementation

MXIbus Timeout Length Shared MXIbus Status/Control Register

(SMSR/SMCR) or EEPROM

MXIbus Fair Requester Shared MXIbus Status/Control Register

(SMSR/SMCR) or EEPROM

MXIbus Parity Checking Shared MXIbus Status/Control Register

(SMSR/SMCR) or EEPROM

VXIbus Model Code

The VXIbus Device Type Register (VDTR) on the VXI-MXI-2 returns

a different model code than the VXI-MXI because it includes new

capabilities and is not an identical replacement for the VXI-MXI.

Required Memory Space

The VXI-MXI-2 register set is too large to fit in its 64-byte VXIbus

configuration area. In addition, you can install onboard DRAM on the

VXI-MXI-2. For both of these reasons the VXI-MXI-2 will request at

least 16 KB of either A24 or A32 space, whereas the VXI-MXI was an

A16-only device. As a result, the VXI-MXI-2 has a VXIbus Offset

Status/Control Register (VSR/VCR).

Sysfail Inhibit

The VXI-MXI-2 provides a Sysfail Inhibit bit in the VXIbus

Status/Control Register (VSR/VCR) to prevent it from asserting the

SYSFAIL* signal as defined by the VXIbus specification. The first-

generation VXI-MXI did not.

VXI-MXI-2 Status/Control Register (VMSR/VMCR)

The Long MXIbus System Controller Timeout bit (LNGMXSCTO) is

no longer implemented. The MXIbus timer of the VXI-MXI-2 is

programmable in the EEPROM and covers an even broader range of

times than the MXIbus timer of the VXI-MXI.