User manual

Appendix D Differences and Incompatibilities between the VXI-MXI and the VXI-MXI-2
VXI-MXI-2 User Manual D-4 © National Instruments Corporation
The Backoff Condition Clear bit (BOFFCLR) is no longer
implemented. It is not necessary because the BKOFF bit in the VXIbus
Interrupt Status Register (VISTR) now clears automatically when read.
The MXTRIGINT, MXSRSTINT, MXACFAILINT, and
MXSYSFINT bits are no longer implemented in the VXI-MXI-2 Status
Register (VMSR). Likewise, the MXTRIGEN, MXSRSTEN, and
MXACFAILEN bits in the VXI-MXI-2 Control Register (VMCR) are
no longer implemented. For more information about these bits, refer to
the following section, Local Interrupt Conditions.
Local Interrupt Conditions
The first-generation MXIbus has a single interrupt line. MXI-2 has
seven interrupt lines, which correspond to the VMEbus interrupt lines.
The VXI-MXI has some interrupt conditions which would assert the
single MXIbus interrupt directly. Since MXI-2 does not have this single
MXIbus interrupt, the register bits that would enable these conditions
are not implemented on the VXI-MXI-2. Specifically, the
MXTRIGINT, MXTRIGEN, MXSRSTINT, MXSRSTEN,
MXACFAILINT, MXACFAILEN, and MXSYSFINT bits in the
VXI-MXI-2 Status/Control Register (VMSR/VMCR) are not
implemented. Also, the entire MXIbus IRQ Configuration Register
(offset 24 hex on the VXI-MXI) is not implemented.
As an alternative, all these interrupt conditions, with the exception of
MXTRIGINT, can be routed to one of the VMEbus interrupt lines,
which then can be routed to the corresponding MXI-2 interrupt line.
Also, the utility signals SYSRESET*, ACFAIL*, and SYSFAIL* can
be routed to MXI-2 to be detected at the destination as a utility signal
rather than generating an interrupt and sending the interrupt to the
destination. In fact, this is the only solution available for the
SYSRESET* signal on the VXI-MXI-2. The VXI-MXI-2 cannot
generate an interrupt from SYSRESET*.
The VXI-MXI-2 also cannot generate an interrupt from any trigger
condition. The TRIGINT and TRIGINTIE bits in the VXIbus Interrupt
Status/Control Register (VISTR/VICTR) are not implemented. Instead,
the VXI-MXI-2 allows the TTL trigger lines to be routed from the
VXIbus to the MXIbus so that the destination receives them as triggers
rather than as an interrupt. Refer to the register descriptions for the
VXIbus Interrupt Configuration Register (VICR), VXIbus Trigger
Configuration Register (VTCR), VXIbus Utility Configuration Register
(VUCR), and VXIbus Interrupt Status/Control Register