User manual

Appendix D Differences and Incompatibilities between the VXI-MXI and the VXI-MXI-2

(VISTR/VICTR) in Chapter 5 for more information on these

alternatives to the local interrupt conditions on the single MXIbus

interrupt line. Notice that these same registers and solutions work on an

Enhanced VXI-MXI when the destination has an INTX connection.

VXIbus Trigger Functionality

The PULSE bit in the VXIbus Trigger Drive Register (VTDR) and the

OMS[2:0], ITS[3:0], ETOEN, OTS[3:0], ETRIG, ASINT*, ASIE,

SSINT*, and SSIE bits in the VXIbus Trigger Mode Selection Register

(VTMSR) are not implemented. Also, the entire Trigger Synchronous

Acknowledge Register (write offset 34 hex on the VXI-MXI) and the

Trigger Asynchronous Acknowledge Register (write offset 36 hex on

the VXI-MXI) are not implemented. The VXI-MXI-2 does not provide

the functionality that these bits control on the VXI-MXI.

Hard Reset

The VXIbus Status/ID Register (VSIDR) on the VXI-MXI-2 is cleared

on a hard reset. This register was unaffected by a hard reset on the

VXI-MXI.

The INTLK bit in the VXI-MXI-2 Status Register (VMSR) is set to the

value stored in the EEPROM on a hard reset. By default, the value is 0.

The INTLK bit was unaffected by a hard reset on the VXI-MXI since it

was an onboard switch.

Soft Reset

The following register bits, which are cleared by a soft reset on the

VXI-MXI, are unaffected by a soft reset on the VXI-MXI-2.

• OE in the VXIbus MODID Register (VMIDR)

• CMODE in the VXI-MXI-2 Status/Control Register

(VMSR/VMCR)

• DTTRIG[7:0] in the VXIbus Trigger Drive Register (VTDR)

• DETRIG[1:0] in the VXIbus Trigger Drive Register (VTDR)

• DIRQ[7:1] in the VXIbus Interrupt Control Register (VICTR)