User manual

Appendix F DMA Programming Examples

/* The following write causes any block transfer to the MXIbus

from either DMA controller to be a synchronous burst transfer by

setting both DMAxMBS bits in the SMCR. You can modify this write

so that both DMA controllers perform normal MXIbus block

transfers, or you can have one DMA controller perform normal

MXIbus block transfers and the other perform synchronous burst

transfers. Remember that MXIbus synchronous burst transfers cannot

be used when both the source and destination are located on the

MXIbus. */

write(A24, A24BASE + SMCR, BYTE, 0x38);

/* The following write is required to initialize the CHCRx for the

DMA controller that will be used. If you will be using both DMA

controllers, perform this write to both CHCR1 and CHCR2. */

write(A24, A24BASE + CHCR1, LONGWORD, 0x00004000);

/************************************************************

* *

* Operation Setup: This section sets up one of the DMA *

* controllers to perform a data transfer from the VMEbus *

* to the MXIbus and starts the operation. Repeat this *

* process for each DMA operation. You can also perform *

* these steps to the other DMA controller to start *

* another operation without waiting for the first one to *

* complete. *

* *

************************************************************/

/* The following write sets up the DMA Source Configuration

and that 32-bit block transfers with the address modifier code

0x3B will be used to access it. Table F-1, at the end of this

appendix, describes the address modifier codes that can be written

to this register. Remember that if the source is DRAM onboard the

VXI-MXI-2, the address modifier code should be written with 0.

This step can be skipped if SCR1 was already written with the same

value from a previous DMA operation. This is useful if you will be

performing several DMA operations where the source device remains

constant. */

write(A24, A24BASE + SCR1, LONGWORD, 0x00E047BB);