User manual

Chapter 2 Functional Overview
© National Instruments Corporation 2-3 VXI-MXI-2 User Manual
• VXIbus Slot 0
Functions
When the VXI-MXI-2 is installed in slot 0 of a VXIbus mainframe
it assumes the Slot 0 responsibilities defined in the VXIbus
specification. These are the VMEbus 16 MHz system clock driver,
VMEbus arbiter, VMEbus IACK daisy-chain driver, VXIbus CLK10
driver, and VXIbus MODID register. All of these functions are
disabled when the VXI-MXI-2 is not acting as the VXIbus Slot 0
device. The VXI-MXI-2 has the ability to automatically detect if it is
installed in slot 0 of a VXIbus. The VXI-MXI-2 does not provide a
power monitor or serial clock driver.
• DMA Controllers 1
and 2
The VXI-MXI-2 has two DMA controllers, which operate
independently of each other. Each DMA controller can be
programmed to move data from any source to any destination. The
source and destination can be located on the VXIbus, MXIbus, or the
VXI-MXI-2 module’s onboard DRAM. The DMA controllers will
direct the MXIbus and VXIbus master state machines to initiate data
transfer cycles on their respective bus and can access the onboard
DRAM directly. The DMA controllers allow different cycle types
and even different data widths between the source and destination
during the DMA transfer.
• MXI-2 System
Controller Functions
The VXI-MXI-2 has the ability to act as the MXI-2 system controller.
When acting as the system controller, the VXI-MXI-2 provides the
MXIbus arbiter, priority-selection daisy-chain driver, and bus timeout
unit. The VXI-MXI-2 can automatically detect from the MXI-2 cable
if it is the system controller.
• VMEbus Control
Signals Transceivers
These transceivers ensure that the VXI-MXI-2 meets the loading,
driving, and timing requirements of the VMEbus specification for the
various control signals.
• VMEbus Master
State Machine
This state machine generates VMEbus master data transfer cycles
when directed to do so by the MXI-2 slave state machine, thus
allowing MXIbus cycles to map to the VXIbus. This state machine
will also generate VMEbus master data transfer cycles when
instructed to do so by one of the DMA controllers. The VXI-MXI-2
can generate D64, D32, D16, and D08(EO) single, block, and RMW
cycles on the VXIbus in A32 and A24 space. All data transfers can
also be generated in A16 space with the exception of D64 and block
transfers. Two consecutive MXIbus slave cycles are required to
generate a single D64 data transfer cycle. The VXI-MXI-2 will not
generate unaligned VMEbus data transfers.