User manual

Appendix F DMA Programming Examples
VXI-MXI-2 User Manual F-10 © National Instruments Corporation
/* The following read generates a 16-bit interrupt acknowledge
cycle for level 5 and stores the Status ID returned in the value
variable. */
read(IACK, LEVEL5, WORD, value);
/* The following if statement checks if the Status ID returned
from the interrupt acknowledge cycle matches the code for the
VXI-MXI-2 module's DMA interrupt condition (assuming the logical
address of the VXI-MXI-2 module is 1). The upper bits of the
Status ID code were written to the DMAISIDR in the Initialization
section of this example. If the expression is false, some other
condition asserted the interrupt. */
if (value == 0x1301) {
/* At this point it is known that the VXI-MXI-2 module's DMA
interrupt condition is the highest priority interrupter because
of the Status ID from the interrupt acknowledge cycle. The
following two sections of code are identical. The first section
applies if DMA controller 1 interrupted, and the second section
applies if DMA controller 2 interrupted. */
/* DMA controller 1 section */
read(A24, A24BASE + CHSR1, LONGWORD, value);
/* The following if statement checks if DMA controller 1 is
currently interrupting. */
if (value & 0x80000000) {
/* At this point it is known that DMA controller 1 is
the interrupter. The DONE and ERROR bits of CHSR1 should
be checked for a successful operation. This could be
handled either here or in the main program after the
interrupt service routine has exited. If handled here,
the value variable already contains a copy of CHSR1. The
following three writes re-arm the DMA interrupt
condition. This must be done because it is possible that
the other DMA controller is also interrupting. Notice
that the overall DMA interrupt in CHCR1 (for DMA
controller 1) is left disabled when the interrupt
service routine exits. It will be re-enabled the next
time DMA controller 1 is started (as shown in the last
write of the operation setup section earlier in this
example). */