User manual

Chapter 2 Functional Overview
VXI-MXI-2 User Manual 2-4 © National Instruments Corporation
• MXI-2 Master State
Machine
This state machine generates MXIbus master data transfer cycles
when directed to do so by the VMEbus slave state machine, thus
allowing VMEbus cycles to map to the MXIbus. This state machine
will also generate MXIbus master data transfer cycles when
instructed to do so by one of the DMA controllers. The VXI-MXI-2
can generate D64, D32, D16, and D08(EO) single, block, RMW, and
synchronous burst cycles on the MXIbus in A32 and A24 space. All
data transfers can also be generated in A16 space with the exception
of D64, block, and synchronous burst transfers. A single VMEbus
D64 data transfer is converted to two consecutive MXIbus data
transfers. Synchronous burst MXIbus cycles can be generated only by
the DMA controllers, not the VMEbus slave state machine. The
MXI-2 master state machine also checks MXIbus parity on read data
received and either returns a BERR* to the VMEbus cycle or stores
an error status when a parity error is detected.
• MXI-2 Control
Signals Transceivers
These transceivers ensure that the VXI-MXI-2 meets the loading,
driving, and timing requirements of the MXI-2 specification for the
various control signals.
• VMEbus Slave State
Machine
This state machine monitors the output of the address decoders and
extender window decoders and responds to VMEbus cycles that are
intended for the VXI-MXI-2. Cycles that map to the Logical Address
decoder access the VXI-MXI-2 registers, while cycles that map to the
A24/A32 decoder access either the VXI-MXI-2 registers or the
onboard DRAM SIMMs. Cycles that map through an extender
window decoder are directed to the MXI-2 master state machine,
effectively mapping the VMEbus cycle to the MXIbus. The
VXI-MXI-2 can accept D32, D16, and D08(EO) single and RMW
VMEbus cycles in A32, A24, and A16 space. The VXI-MXI-2 can
also accept D64 and block VME cycles in A32 and A24 space.
Unaligned VMEbus data transfers are treated as D32 data transfers.