User manual

Chapter 2 Functional Overview

• MXI-2 Slave State

Machine

This state machine monitors the output of the address decoders and

extender window decoders and responds to MXIbus cycles that are

intended for the VXI-MXI-2. Cycles that map to the Logical Address

decoder access the VXI-MXI-2 registers, while cycles that map to the

A24/A32 decoder access either the VXI-MXI-2 registers or the

onboard DRAM SIMMs. Cycles that map through an extender

window decoder are directed to the VMEbus master state machine,

effectively mapping the MXIbus cycle to the VMEbus. The

VXI-MXI-2 can accept D32, D16, and D08(EO) single and RMW

MXIbus cycles in A32, A24, and A16 space. The VXI-MXI-2 can

also accept synchronous, D64, and block MXIbus cycles in A32 and

A24 space. The MXI-2 slave state machine can also convert MXIbus

synchronous and block cycles into single VMEbus cycles for cases

where the destination VMEbus slave device does not support

VMEbus block cycles. The MXI-2 slave state machine checks for

MXIbus parity errors. If a parity error is detected during the address

phase of a cycle, the VXI-MXI-2 ignores the cycle. If a parity error is

detected during the data phase of a write cycle, the MXI-2 slave state

machine responds with a BERR* on the MXIbus.

• VMEbus Bus

Timeout Unit

The VXI-MXI-2 has a VMEbus Bus Timeout Unit (BTO), which

terminates (with BERR*) any VMEbus cycle in which DTACK* or

BERR* are not asserted in a prescribed amount of time after DS* is

asserted. The duration of the timeout is programmably selectable in

the range of 15 µs to 256 ms. Notice that the VXI-MXI-2 must be the

sole bus timer of its VXIbus chassis even when not installed in Slot 0.

This is because the bus timer should not terminate VMEbus cycles

that map to the MXIbus. The MXI-2 bus timer is responsible for

timing these cycles. Therefore, be sure to disable the BTO on all

other modules in each mainframe that has a VXI-MXI-2.

• A24/A32 Decoder This address decoder monitors the VXIbus and MXIbus for access to

the VXI-MXI-2 A24/A32 memory space. All resources located on

the VXI-MXI-2 are accessible in this region. The lowest 4 KB are

directed to the VXI-MXI-2 registers while the remainder maps to the

onboard DRAM SIMMs.

• Logical Address

Decoder

This address decoder monitors the VXIbus and MXIbus for A16

accesses to the VXI-MXI-2 VXIbus configuration space registers

based on its logical address. A subset of the VXI-MXI-2 registers are

accessible in this region, which conforms to VXI-6, the VXIbus

Mainframe Extender Specification.