User manual

Chapter 2 Functional Overview
VXI-MXI-2 User Manual 2-6 © National Instruments Corporation
• MXI-2 Parity Check
and Generation
The MXI-2 parity check/generation circuitry checks for even parity at
any time that the VXI-MXI-2 is receiving the AD[31–0] signals. If
parity is not even, the appropriate MXI-2 state machine is signaled.
The MXI-2 master state machine is signaled for a parity error during
the data phase of a MXIbus master read cycle while the MXI-2 slave
state machine is signaled for a parity error during the address phase
of any MXIbus slave cycle and the data phase of a MXIbus slave
write cycle. Even parity is also generated and sent to the MXIbus
with master address and write data as well as slave read data.
• VMEbus Address
and Address Modifier
Transceivers
These transceivers ensure that the VXI-MXI-2 meets the loading,
driving, and timing requirements of the VMEbus specification for the
A[31–1] and AM[5–0] signals.
• MXI-2 Address/Data
and Address Modifier
Transceivers
These transceivers ensure that the VXI-MXI-2 meets the loading,
driving, and timing requirements of the MXI-2 specification for the
AD[31–0], AM[4–0], and CONVERT* signals.
• A32 Window This address decoder monitors the VXIbus and MXIbus for A32
accesses that map to the opposite bus, and alerts the appropriate state
machines when one occurs. This window behaves as defined in
VXI-6, the VXIbus Mainframe Extender Specification.
• A24 Window This address decoder monitors the VXIbus and MXIbus for A24
accesses that map to the opposite bus, and alerts the appropriate state
machines when one occurs. This window behaves as defined in
VXI-6, the VXIbus Mainframe Extender Specification.
• A16 Window This address decoder monitors the VXIbus and MXIbus for A16
accesses that map to the opposite bus, and alerts the appropriate state
machines when one occurs. This window accepts cycles only within
the lower 48 KB of A16 space. The upper 16 KB (VXIbus
configuration space) cannot be mapped through the A16 window.
This window behaves as defined in VXI-6, the VXIbus Mainframe
Extender Specification.
• LA Window This address decoder monitors the VXIbus and MXIbus for VXIbus
configuration accesses (the upper 16 KB of A16 space) that map to
the opposite bus and alerts the appropriate state machines when one
occurs. This window behaves as defined in VXI-6, the VXIbus
Mainframe Extender Specification.
• MXI-2 Terminate The VXI-MXI-2 has onboard MXI-2 termination circuitry that
automatically detects if it is at either cable end to terminate the
MXIbus signals. The MXI-2 cable is designed to allow this. If the
VXI-MXI-2 is a middle device on the MXIbus, the termination is
disabled.