User manual

Chapter 2 Functional Overview
© National Instruments Corporation 2-7 VXI-MXI-2 User Manual
• VXI-MXI-2
Registers
This logic block represents all registers on the VXI-MXI-2. The
registers are accessible from either the VXIbus or the MXIbus. All
registers are available in the first 4 KB of the VXI-MXI-2 A24/A32
memory space, while a subset is accessible in the VXI-MXI-2
VXIbus A16 configuration area.
• Onboard DRAM
SIMMs
This logic block represents the two DRAM SIMM sockets on the
VXI-MXI-2. If DRAM is installed, it will be accessible in the
VXI-MXI-2 A24/A32 memory space that is not mapped to registers
(above 4 KB).
• VMEbus Data
Transceivers
These transceivers ensure that the VXI-MXI-2 meets the loading,
driving, and timing requirements of the VMEbus specification for the
D[31–0] signals.
• VMEbus Interrupt
and Utility Signal
Transceivers
These transceivers ensure that the VXI-MXI-2 meets the loading,
driving, and timing requirements of the VMEbus specification for the
IRQ*[7–1], SYSRESET*, SYSFAIL*, and ACFAIL* signals.
• Interrupt and Utility
Signal Circuitry
This circuitry handles mapping of the interrupt and utility signals
between the VXIbus and MXIbus. The utility signals include
SYSRESET*, SYSFAIL*, and ACFAIL*. This circuitry also
generates interrupts from other conditions on the VXI-MXI-2 and
allows generation of the utility signals.
• MXI-2 Interrupt and
Utility Signal
Transceivers
These transceivers ensure that the VXI-MXI-2 meets the loading,
driving, and timing requirements of the MXI-2 specification for the
IRQ*[7–1], SYSRESET*, SYSFAIL*, and ACFAIL* signals.
• VXIbus CLK10 and
TTL & ECL Trigger
Transceivers
These transceivers ensure that the VXI-MXI-2 meets the loading,
driving, and timing requirements of the VXIbus specification for the
CLK10±, TTLTRIG[7–0], and ECLTRIG[1–0] signals.
• CLK10 and Trigger
Circuitry
This circuitry handles mapping of the CLK10 and TTL trigger lines
between the VXIbus and MXIbus. CLK10 and TTL triggers, in
addition to ECL triggers, can also be mapped to or from the front
panel SMB connectors. This circuitry also allows the VXI-MXI-2 to
source the TTL and ECL trigger lines and to generate an interrupt on
various trigger conditions.
• MXI-2 CLK10 AND
Trigger Transceivers
These transceivers ensure that the VXI-MXI-2 meets the loading,
driving, and timing requirements of the MXI-2 specification for the
CLK10± and TRIGGER±[7–0] signals.
• SMB Transceivers These transceivers are used for the front panel SMB signals
EXT CLK, Trigger Out, and Trigger In. The VXI-MXI-2 can also
terminate the Trigger In and EXT CLK (when receiving) signals
with 50 Ω.