User manual

Index
VXI-MXI-2 User Manual Index - 4 © National Instruments Corporation
TRGOUT, 5-36
TRIG[7:0], 5-34
TRIGDIR[7:0], 5-42
TRIGEN[7:0], 5-42
TRIGINT, D-4
TRIGINTIE, D-4
TSIZE[1:0], 5-74, 5-79
TTL*, 5-23
TTLTRGDIR[7:0], 5-22
TTLTRGEN[7:0], 5-22
UTIL*, 5-24
VERSION[3:0], 5-7
XFERR, 5-83
BKOFF bit, 5-37, D-4
BKOFFIE bit, 5-39
BLOCKEN bit
DMA Destination Configuration
Register (DCRx), 5-78
DMA Source Configuration Register
(SCRx), 5-73
BOFFCLR bit, D-4
BTO. See Bus Timeout (BTO).
bulletin board support, H-1
Bus Timeout (BTO)
MXIbus, 7-11, B-8
VMEbus, 2-5, B-5, E-9
VXIbus, 7-8
C
cables for MXIbus, connecting
VXI-MXI-2, 3-20
VXI-MXI-2/B, 4-19
CLK10 signal
transceivers, 2-7
trigger circuitry, 2-7
trigger transceivers, 2-7
CLK10 signal configuration, MXIbus, 7-13
CLK10 signal configuration, VXIbus
routing for two-frame system,
E-6 to E-8
VXI-MXI-2, 3-7 to 3-11
CLK10 generated from MXIbus
(figure), 3-8
CLK10 generated from onboard
oscillator (figure), 3-8
CLK10 generated from SMB
(figure), 3-8
drive inverted external CLK SMB
(figure), 3-10
drive non-inverted external CLK
SMB (figure), 3-10
receive external CLK SMB
(figure), 3-10
receive external CLK SMB with
50 Ω termination (figure), 3-10
receiving or driving MXIbus
CLK10 (figure), 3-11
VXI-MXI-2/B, 4-7 to 4-11
CLK10 generated from MXIbus
(figure), 4-8
CLK10 generated from onboard
oscillator (figure), 4-8
CLK10 generated from SMB
(figure), 4-8
drive inverted external CLK SMB
(figure), 4-10
drive non-inverted external CLK
SMB (figure), 4-10
receive external CLK SMB
(figure), 4-10
receive external CLK SMB with
50 Ω termination (figure), 4-10
receiving or driving MXIbus
CLK10 (figure), 4-11
CLR DMAIE bit, 5-68
CLR DONEIE bit, 5-69
CLRDONE bit, 5-65
CMODE bit
soft reset, D-5
VXI-MXI-2 Control Register (VMCR),
5-30 to 5-31
VXI-MXI-2 Status Register
(VMSR), 5-27
configuration
CLK10 signal. See CLK10 signal
configuration.