User manual
Index
© National Instruments Corporation Index
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5 VXI-MXI-2 User Manual
system configuration. See system
configuration.
two-frame system. See configuration of
two-frame system.
VXI-MXI and VXI-MXI-2 differences
and incompatibilities, D-2
VXI-MXI-2, 3-1 to 3-20
damage from electrostatic
discharge (warning), 3-1
MXIbus termination, 3-13 to 3-14
onboard DRAM, 3-17 to 3-18
removing metal enclosure, 3-3
right-side cover of VXI-MXI-2
(figure), 3-2
trigger input termination, 3-12
VXIbus CLK10 routing,
3-7 to 3-11
VXIbus local bus, 3-6 to 3-7
VXIbus logical address, 3-3 to 3-4
VXIbus Slot 0/non-Slot 0,
3-5 to 3-6
VXI-MXI-2/B, 4-1 to 4-19
damage from electrostatic
discharge (warning), 4-1
MXIbus termination, 4-12 to 4-13
onboard DRAM, 4-16 to 4-17
parts locator diagram, 4-2
trigger input termination, 4-12
VXIbus CLK10 routing,
4-7 to 4-11
VXIbus local bus, 4-6 to 4-7
VXIbus logical address, 4-3 to 4-4
VXIbus Slot 0/non-Slot 0,
4-5 to 4-6
configuration EEPROM. See EEPROM
configuration.
configuration of two-frame system,
E-1 to E-9
hardware switches required (figure)
VXI-MXI-2, E-3
VXI-MXI-2/B, E-4
MXIbus System Controller, E-8
two-frame VXI system (figure), E-2
VMEbus BTO unit, E-9
VXIbus CLK10 routing, E-6 to E-8
VXIbus logical address, E-4 to E-5
VXIbus Slot 0, E-8
connectors
external clock connector, C-6 to C-7
EXT CLK connector (figure), C-6
EXT CLK signal characteristics
(table), C-7
MXI-2 connector (figure), C-4
MXI-2 connector signal assignments
(table), C-4 to C-5
trigger input connector, C-8
TRG IN connector (figure), C-8
TRG IN signal characteristics
(table), C-8
trigger output connector, C-7
TRG OUT (figure), C-7
TRG OUT signal characteristics
(table), C-7
VXI-MXI and VXI-MXI-2 differences
and incompatibilities, D-1 to D-2
control signals transceivers
MXI-2, 2-4
VMEbus, 2-3
cover of VXI-MXI-2
removing metal enclosure, 3-3
right-side cover of VXI-MXI-2
(figure), 3-2
customer communication, xvi, H-1 to H-2
D
DA[31:0] bits, 5-80 to 5-81
data and address modifier transceivers,
MXI-2, 2-6
data transceivers, VMEbus, 2-7
decoder
A24/A32, 2-5
logical address, 2-5
DERR[1:0] bits, 5-84
DETRIG[1:0] bits, 5-35, D-5
DEVCLASS[1:0] bits, 5-4
DIRQ[7:1] bits, 5-40, D-5