User manual

Index
VXI-MXI-2 User Manual Index - 8 © National Instruments Corporation
I7[15:0] bits, 5-49
ILVL[2:0] bits, 5-54
installation. See also configuration.
requirements for VXI-MXI-2 interfaces,
6-3
VXI-MXI-2
connecting MXIbus cable, 3-20
damage from electrostatic
discharge (warning), 3-1
general instructions, 3-19
VXI-MXI-2/B
connecting MXIbus cable, 4-19
damage from electrostatic
discharge (warning), 4-1
general instructions, 4-18
INT bit, 5-82
INTDIR[7:1] bits, 5-21
INTEN[7:1] bits, 5-20
interlocked arbitration mode, 7-5 to 7-6, B-9
interrupt and utility signal circuitry, 2-7
interrupt and utility signal transceivers
MXI-2, 2-7
VMEbus, 2-7
interrupt conditions, local, D-4 to D-5
INTLCK bit
enabling interlocked arbitration mode,
7-6
VXI-MXI-2 Control Register (VMCR),
5-32
VXI-MXI-2 Status Register (VMSR),
5-28
INTLK bit, D-5
INTX enhancement for VXI-MXI, D-1
IOCONFIG bit, 5-59
IRQ[7:1] bits, 5-38
ISTAT bit, 5-53
ITS[3:0] bits, D-5
J
jumper and switch settings
two-frame system
CLK10 routing, E-6 to E-8
VXIbus logical address, E-4 to E-5
VXI-MXI and VXI-MXI-2 differences
and incompatibilities, D-2 to D-3
VXI-MXI-2
EEPROM, 3-15 to 3-16
MXIbus termination, 3-13 to 3-14
onboard DRAM, 3-17 to 3-18
trigger input termination, 3-12
VXIbus CLK10 routing,
3-7 to 3-11
VXIbus local bus, 3-6 to 3-7
VXIbus logical address, 3-4
VXIbus Slot 0/non-Slot 0, 3-5
VXI-MXI-2/B
EEPROM, 4-14 to 4-15
MXIbus termination, 4-12 to 4-13
onboard DRAM, 4-16 to 4-17
trigger input termination, 4-12
VXIbus CLK10 routing,
4-7 to 4-11
VXIbus local bus, 4-6 to 4-7
VXIbus logical address, 4-4
VXIbus Slot 0/non-Slot 0, 4-5
L
LA window. See logical address (LA)
window.
LA[7:0] bits, 5-34
LABASE[7:0] bits, 5-13
LADIR bit, 5-13
LAEN bit, 5-12
LASIZE[2:0] bits, 5-13
LINT[3:1] bits
VXIbus Interrupt Control Register
(VICTR), 5-39
VXIbus Interrupt Status Register
(VISTR), 5-37