User manual

Index
VXI-MXI-2 User Manual Index - 10 © National Instruments Corporation
mnemonics key, G-1 to G-9
MODEL[11:0] bits, 5-5
MODID* bit, 5-6
MODID[12:0]bits, 5-11
multiframe RM
multiframe RM in VXIbus mainframe
(figure), 6-3
multiframe RM on PC (figure), 6-2
overview, 6-1
tree topologies, 6-1
multiframe RM operation, 6-39 to 6-44
configuring A24 and A32 addressing
windows, 6-44
configuring logical address window,
6-39 to 6-40
example, 6-40 to 6-43
logical address assignments for example
VXIbus/MXIbus system (table), 6-41
system administration and
initiation, 6-44
MXACFAILEN bit, D-4
MXACFAILINT bit, D-4
MXI-2. See also VXI-MXI-2.
address/data and address modifier
transceivers, 2-6
control signals transceivers, 2-4
description, 1-2
interrupt and utility signal
transceivers, 2-7
master state machine, 2-4
parity check and generation, 2-6
slave state machine, 2-5
System Controller, 2-3
termination, 2-6
MXI-2 connector
figure, C-4
signal assignments (table), C-4 to C-5
VXI-MXI and VXI-MXI-2 differences
and incompatibilities, D-1 to D-2
MXIbus
capability descriptions, A-1
connecting MXIbus cable
VXI-MXI-2, 3-20
VXI-MXI-2/B, 4-19
fair requester, B-9
parity checking, B-9
signal characteristics (table), C-6
System Controller, 2-3, E-8
termination
VXI-MXI-2, 3-13 to 3-14
VXI-MXI-2/B, 4-12 to 4-13
timer limit, B-8
MXIbus configuration options
auto retry, 7-12
bus timeout, 7-11
CLK10, 7-13
fair requester, 7-12
illustration, 7-10
parity checking, 7-12
System Controller, 7-11
transfer limit, 7-11
MXISC bit, 5-28
MXSCTO bit, 5-28
MXSRSTEN bit, D-4
MXSRSTINT bit, D-4
MXSYSFINT bit, D-4
MXTRIGEN bit, D-4
MXTRIGINT bit, D-4
N
non-Slot 0 configuration, VXIbus
VXI-MXI-2, 3-5 to 3-6
VXI-MXI-2/B, 4-5 to 4-6
O
OE bit, D-5
OFFSET[15:0] bits, 5-10
OMS[2:0] bits, D-5
onboard DRAM
avoiding first 4 KB of memory space
(caution), 7-4, B-3
configuration, VXI-MXI-2,
3-17 to 3-18
SIMM size configuration
(figure), 3-17
VXI-MXI-2 DRAM configurations
(table), 3-18