User manual

Index
© National Instruments Corporation Index - 13 VXI-MXI-2 User Manual
multiframe RM in VXIbus
mainframe (figure), 6-3
multiframe RM on PC (figure), 6-2
required logical addresses for
example VXIbus/MXIbus system
(table), 6-7
steps to follow, 6-6 to 6-11
worksheets for VXIbus/MXIbus A16
address map
A16 space address map
diagram, 6-33
MXIbus #1 A16 address map, 6-35
MXIbus #1 of example A16
address map, 6-30 to 6-31
MXIbus #2 A16 address map, 6-36
MXIbus #3 A16 address map, 6-37
MXIbus #3 of example A16
address map, 6-32
MXIbus #4 A16 address map, 6-38
summary of A16 address map
blank form, 6-34
example, 6-29
worksheets for VXIbus/MXIbus logical
address map
alternative worksheets,
6-20 to 6-22
logical address map diagram for
VXIbus/MXIbus system, 6-15
MXIbus #1 of example
VXIbus/MXIbus system, 6-13
MXIbus #1 of VXIbus/MXIbus
system, 6-17
MXIbus #2 of example
VXIbus/MXIbus system, 6-14
MXIbus #2 of VXIbus/MXIbus
system, 6-18
MXIbus #3 of example
VXIbus/MXIbus system, 6-14
MXIbus #3 of VXIbus/MXIbus
system, 6-19
summary of example
VXIbus/MXIbus system, 6-12
summary of VXIbus/MXIbus
system, 6-16
System Controller
MXI-2, configuring, 7-11
VXIbus
configuring, 7-7 to 7-8
installing in different slot
(warning), 7-8
System Controller, MXIbus, 2-3, E-8
T
TC[31:0] bits, 5-70 to 5-71
technical support, H-1 to H-2
termination
MXI-2, 2-6
VXI-MXI-2
MXIbus, 3-13 to 3-14
trigger input, 3-12
VXI-MXI-2/B
MXIbus, 4-12 to 4-13
trigger input, 4-12
timeout
bus. See Bus Timeout (BTO).
VMEbus arbiter, B-6
VXIbus arbiter, 7-9
timer limit
MXIbus, B-8
VMEbus, B-5
transceivers
CLK10 and trigger transceivers, 2-7
MXI-2
address/data and address modifier
transceivers, 2-6
control signal transceivers, 2-4
interrupt and utility signal
transceivers, 2-7
SMB transceivers, 2-7
VMEbus
address and address modifier
transceivers, 2-6
control signal transceivers, 2-3
data transceivers, 2-7
interrupt and utility signal
transceivers, 2-7
VXIbus CLK10 and TTL and ECL
trigger transceivers, 2-7