User manual

Index
VXI-MXI-2 User Manual Index - 14 © National Instruments Corporation
transfer limit, configuring
MXIbus, 7-11
VXIbus, 7-9
TRGIN bit, 5-36
TRGOUT bit, 5-36
TRIG[7:0] bits, 5-34
TRIGDIR[7:0] bits, 5-42
TRIGEN[7:0] bits, 5-42
trigger circuitry, CLK10, 2-7
trigger input connector, C-8
TRG IN connector (figure), C-8
TRG IN signal characteristics
(table), C-8
trigger output connector, C-7
TRG OUT (figure), C-7
TRG OUT signal characteristics
(table), C-7
triggers
CLK10 and trigger transceivers, 2-7
CLK10 and TTL and ECL trigger
transceivers, 2-7
input termination
VXI-MXI-2, 3-12
VXI-MXI-2/B, 4-12
VXIbus functionality, D-5
TRIGINT bit, D-4
TRIGINTIE bit, D-4
TSIZE[1:0] bits
DMA Destination Configuration
Register (DCRx), 5-79
DMA Source Configuration Register
(SCRx), 5-74
TTL* bit, 5-23
TTLTRGDIR[7:0] bits, 5-22
TTLTRGEN[7:0] bits, 5-22
two-frame system. See configuration of
two-frame system.
U
UTIL* bit, 5-24
V
VERSION[3:0] bits, 5-7
VMEbus
Bus Timeout (BTO)
for two-frame system, E-9
overview, 2-5
VMEbus timer limit, B-5
capability codes, A-2
control signals transceivers, 2-3
data transceivers, 2-7
interrupt and utility signal
transceivers, 2-7
master state machine, 2-3
slave state machine, 2-4
timer limit, B-5
VMEbus arbiter
arbiter timeout, B-6
arbiter type, B-6
VMEbus requester
fair request, B-7
request level, B-7
VXIbus A24/A32 Registers
DMA Channel Control Register
(CHCRx), 5-68 to 5-69
DMA Channel Operation Register
(CHORx), 5-65 to 5-67
DMA Channel Status Register
(CHSRx), 5-82 to 5-84
DMA Destination Address Register
(DARx), 5-80 to 5-81
DMA Destination Configuration
Register (DCRx), 5-77 to 5-79
DMA FIFO Count Register
(FCRx), 5-85
DMA Interrupt Configuration Register
(DMAICR), 5-52 to 5-54
DMA Interrupt Enable Register
(DMAIER), 5-55 to 5-56
DMA Interrupt Status/ID Register
(DMAISDR), 5-57 to 5-58