User manual

Chapter 5 Register Descriptions

8 ACCDIR Access Direction

This bit returns a 1 when it is read from the

MXIbus. When this bit is read from the VXIbus

it returns a 0.

7-4 VERSION[3:0] Version Number

These bits indicate the revision of the

VXI-MXI-2 as shown below. These bits are not

affected by hard or soft resets.

VERSION (3:0)

Value (Hex)

VXI-MXI-2

Revision

3 READY Ready

This bit becomes 1 shortly after a hard reset to

indicate that the VXI-MXI-2 is ready to execute

all of its functionality. This bit is not affected by

a soft reset.

2 PASSED Passed

This bit becomes 1 shortly after a hard reset to

indicate that the VXI-MXI-2 has completed

its power-on initialization sequence. The

VXI-MXI-2 asserts the SYSFAIL* line on the

VXIbus after a hard reset until this bit becomes

1. This bit is not affected by a soft reset.

1 SFINH Sysfail Inhibit

This bit reflects the state of the SFINH bit in the

VXIbus Control Register (VCR).

0 RESET Soft Reset

This bit reflects the state of the RESET bit in the

VXIbus Control Register (VCR).