User manual

Chapter 5 Register Descriptions
VXI-MXI-2 User Manual 5-8 © National Instruments Corporation
VXIbus Control Register (VCR)
VXIbus Configuration Offset: 4 (hex)
Attributes: Write Only 32, 16, 8-bit accessible
15 14 13 12 11 10 9 8
A24/A32
ENABLE
XXXXXXX
76 54 321 0
X X X X X X SFINH RESET
This register provides various control bits for the VXI-MXI-2. This register conforms to
the VXIbus specification. When accessed with a 32-bit cycle, the bits of this register
appear on bits 31 to 16 along with the VXIbus Offset Register (VOR) on bits 15 to 0.
Bit Mnemonic Description
15 A24/A32 ENABLE A24/A32 Enable
Writing a 1 to this bit enables the A24/A32
address decoding on the VXI-MXI-2. When this
bit is 0 the VXI-MXI-2 does not respond to
accesses to its onboard A24/A32 resources. This
bit is cleared on a hard reset and is not affected
by a soft reset.
14-2 X Reserved
These bits are reserved. Write each of these bits
with 1 when writing to the VCR.
1 SFINH Sysfail Inhibit
Writing a 1 to this bit disables the VXI-MXI-2
from asserting the SYSFAIL* line due to its
PASSED bit in the VXIbus Status Register
(VSR) being clear. The VXI-MXI-2 is still able
to assert SYSFAIL* if the DSYSFAIL bit in the
VXI-MXI-2 Control Register (VMCR) is set or
if SYFAIL* is mapped from the MXIbus to the
VXIbus regardless of the state of this bit. This bit
is cleared on a hard reset and is not affected by a
soft reset.